From: Thierry Reding <treding@nvidia.com>
To: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Cc: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
jgg@nvidia.com, iommu@lists.linux.dev,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] iommu: map reserved memory as cacheable if device is coherent
Date: Wed, 20 Sep 2023 12:17:46 +0200 [thread overview]
Message-ID: <ZQrGyqQ7K96PFXQ1@orome> (raw)
In-Reply-To: <20230914125258.19640-1-laurentiu.tudor@nxp.com>
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On Thu, Sep 14, 2023 at 03:52:58PM +0300, Laurentiu Tudor wrote:
> Check if the device is marked as DMA coherent in the DT and if so,
> map its reserved memory as cacheable in the IOMMU.
> This fixes the recently added IOMMU reserved memory support which
> uses IOMMU_RESV_DIRECT without properly building the PROT for the
> mapping.
>
> Fixes: a5bf3cfce8cb ("iommu: Implement of_iommu_get_resv_regions()")
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
> ---
> Changes in v2:
> - added Reviewed-by tag
>
> drivers/iommu/of_iommu.c | 3 +++
> 1 file changed, 3 insertions(+)
Acked-by: Thierry Reding <treding@nvidia.com>
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prev parent reply other threads:[~2023-09-20 10:17 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-14 12:52 [PATCH v2] iommu: map reserved memory as cacheable if device is coherent Laurentiu Tudor
2023-09-20 10:17 ` Thierry Reding [this message]
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