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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, Luca Coelho <luciano.coelho@intel.com>
Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915: Require FEC for DSC on DP-MST
Date: Wed, 20 Sep 2023 14:09:07 +0300	[thread overview]
Message-ID: <ZQrS0_ZGNLihp397@intel.com> (raw)
In-Reply-To: <87led1ryj0.fsf@intel.com>

On Wed, Sep 20, 2023 at 12:20:51PM +0300, Jani Nikula wrote:
> On Wed, 13 Sep 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The current check just asserts that we need FEC to use DSC
> > with (non-eDP) DP-SST. But MST also needs FEC for DSC. Just
> > check for !eDP instead to cover all the cases correctly.
> 
> 128b/132b won't have crtc->fec_enable set, as it's part of channel
> encoding. We don't need to explicitly enable it in hardware, the
> 128b/132b bandwidth computations take it into account in the equation,
> but we can't skip DSC based on !crtc_state->fec_enable either.

Hmm. Right. I suppose we need a uhbr check here as well then.

> 
> BR,
> Jani.
> 
> 
> >
> > Cc: Luca Coelho <luciano.coelho@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 2cde8ac513bb..41f180f2879e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1380,7 +1380,7 @@ static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> >  static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> >  				  const struct intel_crtc_state *crtc_state)
> >  {
> > -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
> > +	if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable)
> >  		return false;
> >  
> >  	return intel_dsc_source_support(crtc_state) &&
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2023-09-20 11:09 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-13 15:03 [Intel-gfx] [PATCH 1/2] drm/i915: Check lane count when determining FEC support Ville Syrjala
2023-09-13 15:03 ` [Intel-gfx] [PATCH 2/2] drm/i915: Require FEC for DSC on DP-MST Ville Syrjala
2023-09-20  9:20   ` Jani Nikula
2023-09-20 11:09     ` Ville Syrjälä [this message]
2023-10-04 15:36   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2023-09-13 23:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Check lane count when determining FEC support Patchwork
2023-09-14  3:27 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-09-20  9:23 ` [Intel-gfx] [PATCH 1/2] " Jani Nikula
2023-09-20 11:14   ` Ville Syrjälä
2023-09-20 12:01     ` Jani Nikula
2023-10-04 22:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Check lane count when determining FEC support (rev2) Patchwork
2023-10-05  9:24 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-10-05 13:13 ` [Intel-gfx] [PATCH 1/2] drm/i915: Check lane count when determining FEC support Imre Deak

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