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From: Leo Liang <ycliang@andestech.com>
To: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Cc: Rick Chen <rick@andestech.com>, <u-boot@lists.denx.de>
Subject: Re: [PATCH 1/1] cmd/exception: test RISC-V 16 bit aligned instruction
Date: Tue, 26 Sep 2023 15:48:05 +0800	[thread overview]
Message-ID: <ZRKMtePGvtPCTAbb@swlinux02> (raw)
In-Reply-To: <20230921103929.86836-1-heinrich.schuchardt@canonical.com>

On Thu, Sep 21, 2023 at 12:39:29PM +0200, Heinrich Schuchardt wrote:
> A 16 bit aligned instruction should generated an exception if the C
> extension is not available.
> 
> Provide an 'extension ialign16' command for testing exception handling.
> 
> For testing build qemu-riscv64_defconfig with CONFIG_RISCV_ISA_C=n
> and run with
> 
>     qemu-system-riscv64 -M virt -bios u-boot -nographic -cpu rv64,c=false
> 
>     => exception ialign16
>     Unhandled exception: Instruction address misaligned
>     EPC: 0000000087719138 RA: 0000000087719218 TVAL: 000000008771913e
>     EPC: 0000000080020138 RA: 0000000080020218 reloc adjusted
> 
>     Code: 0113 0101 8067 0000 0113 ff01 3423 0011 (006f 0060)
> 
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> ---
>  cmd/riscv/exception.c | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

      reply	other threads:[~2023-09-26  7:49 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-21 10:39 [PATCH 1/1] cmd/exception: test RISC-V 16 bit aligned instruction Heinrich Schuchardt
2023-09-26  7:48 ` Leo Liang [this message]

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