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From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>,
	Dirk Behme <dirk.behme@de.bosch.com>,
	linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH] clk: renesas: rcar-gen3: Extend SDn divider table
Date: Tue, 26 Sep 2023 09:48:19 +0200	[thread overview]
Message-ID: <ZRKMww5Lq9L+PDic@shikoro> (raw)
In-Reply-To: <ZQv4SY8VUXMZ600S@ninjato>

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> > An alternative would be to let cpg_sdh_clk_register() sanitize the
> > pre-existing contents of the SD-IFn Clock Frequency Control Register,
> > so there would be no need to extend cpg_sdh_div_table[].  An advantage
> > of that approach would be that it can handle all invalid combinations,
> > not just the few that have been seen in the wild.
> > (following the old networking mantra: "be strict when sinding, be
> > liberal when receiving').
> 
> That sounds very reasonable to me.

Thinking further: Sanitizing a pre-existing value of SDH means also
sanitizing the value of SD because only specific combinations of these
are recommended (or even "allowed" as I read it). This is getting a bit
complicated. What about just applying a default value to SDH and SD
which is from the recommended set of parameters? That will also help
when probing the clocks. Once SDHI probes, it will modify clocks anyhow.

Opinions?


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  reply	other threads:[~2023-09-26  7:48 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-19 12:37 [PATCH] clk: renesas: rcar-gen3: Extend SDn divider table Dirk Behme
2023-09-20 20:41 ` Wolfram Sang
2023-09-21  4:28   ` Behme Dirk (CM/ESO2)
2023-09-21  7:59     ` Wolfram Sang
2023-09-21  7:52   ` Geert Uytterhoeven
2023-09-21  8:01     ` Wolfram Sang
2023-09-26  7:48       ` Wolfram Sang [this message]
2023-09-26  7:59         ` Geert Uytterhoeven
2023-09-26  8:03           ` Geert Uytterhoeven

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