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X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2023 03:53:00.2317 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: dai3FkxHWojG7YB0h51j2OVbNX7wA3R4DsGNc6sSqvb0v8+1vaeXZdnNmqwJTF/DXmtEJBlycpFjW3Tqy/WT2g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7126 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander.Deucher@amd.com, christian.koenig@amd.com, amd-gfx@lists.freedesktop.org Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On 10/06/ , Yifan Zhang wrote: > add hub->ctx_distance when read CONTEXT1_CNTL, align w/ > write back operation. > > v2: fix coding style errors reported by checkpatch.pl (Christian) > > Signed-off-by: Yifan Zhang > Acked-by: Christian König Reviewed-by: Lang Yu > --- > drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c | 2 +- > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 +- > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 3 ++- > drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 2 +- > drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 2 +- > drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c | 2 +- > drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c | 2 +- > drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 2 +- > drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c | 2 +- > drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 2 +- > drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 2 +- > drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c | 2 +- > drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c | 2 +- > drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c | 2 +- > drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c | 2 +- > drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c | 2 +- > drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 2 +- > 17 files changed, 18 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c > index bcb6ba03cead..f9949fedfbb9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c > @@ -297,7 +297,7 @@ static void gfxhub_v11_5_0_setup_vmid_config(struct amdgpu_device *adev) > uint32_t tmp; > > for (i = 0; i <= 14; i++) { > - tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i); > + tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance); > tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, > adev->vm_manager.num_level); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > index cdc290a474a9..53a2ba5fcf4b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c > @@ -260,7 +260,7 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) > block_size -= 9; > > for (i = 0; i <= 14; i++) { > - tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i); > + tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i * hub->ctx_distance); > tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, > num_level); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c > index ff60670b8464..55423ff1bb49 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c > @@ -329,7 +329,8 @@ static void gfxhub_v1_2_xcc_setup_vmid_config(struct amdgpu_device *adev, > for_each_inst(j, xcc_mask) { > hub = &adev->vmhub[AMDGPU_GFXHUB(j)]; > for (i = 0; i <= 14; i++) { > - tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL, i); > + tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL, > + i * hub->ctx_distance); > tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, > num_level); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > index 8521c45e8f38..793faf62cb07 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c > @@ -287,7 +287,7 @@ static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) > uint32_t tmp; > > for (i = 0; i <= 14; i++) { > - tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); > + tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i * hub->ctx_distance); > tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, > adev->vm_manager.num_level); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c > index f829c441640a..cd0e8a321e46 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c > @@ -296,7 +296,7 @@ static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev) > uint32_t tmp; > > for (i = 0; i <= 14; i++) { > - tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i); > + tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i * hub->ctx_distance); > tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, > adev->vm_manager.num_level); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c > index 89ff7910cb0f..abe30c8bd2ba 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c > @@ -294,7 +294,7 @@ static void gfxhub_v3_0_setup_vmid_config(struct amdgpu_device *adev) > uint32_t tmp; > > for (i = 0; i <= 14; i++) { > - tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i); > + tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance); > tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, > adev->vm_manager.num_level); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c > index be1da5927910..b3ef6e71811f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c > @@ -299,7 +299,7 @@ static void gfxhub_v3_0_3_setup_vmid_config(struct amdgpu_device *adev) > uint32_t tmp; > > for (i = 0; i <= 14; i++) { > - tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i); > + tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance); > tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, > adev->vm_manager.num_level); > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c > index fb91b31056ca..843219a91736 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c > @@ -242,7 +242,7 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) > block_size -= 9; > > for (i = 0; i <= 14; i++) { > - tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i); > + tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i * hub->ctx_distance); > tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, > num_level); > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c > index 9086f2fdfaf4..92432cd2c0c7 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c > @@ -274,7 +274,7 @@ static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev) > block_size -= 9; > > for (i = 0; i <= 14; i++) { > - tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i); > + tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i * hub->ctx_distance); > tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, > num_level); > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c > index 784c4e077470..2c0419faf8d4 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c > @@ -344,7 +344,7 @@ static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev) > hub = &adev->vmhub[AMDGPU_MMHUB0(j)]; > for (i = 0; i <= 14; i++) { > tmp = RREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT1_CNTL, > - i); > + i * hub->ctx_distance); > tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c > index 37458f906980..02fd45261399 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c > @@ -367,7 +367,7 @@ static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev) > uint32_t tmp; > > for (i = 0; i <= 14; i++) { > - tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i); > + tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i * hub->ctx_distance); > tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, > adev->vm_manager.num_level); > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c > index 4ddd9448e2bc..5eb8122e2746 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c > @@ -285,7 +285,7 @@ static void mmhub_v2_3_setup_vmid_config(struct amdgpu_device *adev) > uint32_t tmp; > > for (i = 0; i <= 14; i++) { > - tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i); > + tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i * hub->ctx_distance); > tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, > adev->vm_manager.num_level); > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c > index 9627df8b194b..7d5242df58a5 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c > @@ -323,7 +323,7 @@ static void mmhub_v3_0_setup_vmid_config(struct amdgpu_device *adev) > uint32_t tmp; > > for (i = 0; i <= 14; i++) { > - tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i); > + tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance); > tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, > adev->vm_manager.num_level); > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c > index 77bff803b452..134c4ec10887 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c > @@ -310,7 +310,7 @@ static void mmhub_v3_0_1_setup_vmid_config(struct amdgpu_device *adev) > uint32_t tmp; > > for (i = 0; i <= 14; i++) { > - tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i); > + tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance); > tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, > adev->vm_manager.num_level); > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c > index d1fc9dce7151..f0f182f033b9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c > @@ -315,7 +315,7 @@ static void mmhub_v3_0_2_setup_vmid_config(struct amdgpu_device *adev) > uint32_t tmp; > > for (i = 0; i <= 14; i++) { > - tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i); > + tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance); > tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, > adev->vm_manager.num_level); > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c > index 3d80a184ce6b..76b12f015d1d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c > @@ -303,7 +303,7 @@ static void mmhub_v3_3_setup_vmid_config(struct amdgpu_device *adev) > uint32_t tmp; > > for (i = 0; i <= 14; i++) { > - tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i); > + tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance); > tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, > adev->vm_manager.num_level); > diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c > index 5718e4d40e66..1b7da4aff2b8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c > +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c > @@ -308,7 +308,7 @@ static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid) > > for (i = 0; i <= 14; i++) { > tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL, > - hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i); > + hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i * hub->ctx_distance); > tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, > ENABLE_CONTEXT, 1); > tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL, > -- > 2.37.3 >