From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-210.mta0.migadu.com (out-210.mta0.migadu.com [91.218.175.210]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4DDC630F88 for ; Wed, 11 Oct 2023 16:17:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="rqE+CVVT" Date: Wed, 11 Oct 2023 16:17:13 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1697041038; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=r1TLZrOHuYKUtJ/M2uZHzGl+dSoKy/pyNUOh8kO6hmI=; b=rqE+CVVT2d4VnEpkg/WhSs+a/hq3+0Q0y+MNQ0p8wgUkhodiArjMHYMBiaZ62G1tAZah3G zRwS0RAIXABn7Q986UuguRhcw35DOzgRzoYnSb0aw5NisuAx/kAbeCexl1SgI1jvFwaFeJ GCCP8RqDH4LBfPM/mev9PUK9x2IfJio= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Suzuki K Poulose Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, Marc Zyngier , James Morse , Zenghui Yu , Raghavendra Rao Ananta , Mark Rutland , Will Deacon , James Clark Subject: Re: [PATCH 2/2] KVM: arm64: Treat PMEVTYPER_EL0.NSH as RES0 Message-ID: References: <20231011081649.3226792-1-oliver.upton@linux.dev> <20231011081649.3226792-3-oliver.upton@linux.dev> <24d7dda6-888c-141e-3aa0-9319987360d7@arm.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <24d7dda6-888c-141e-3aa0-9319987360d7@arm.com> X-Migadu-Flow: FLOW_OUT On Wed, Oct 11, 2023 at 01:33:16PM +0100, Suzuki K Poulose wrote: [...] > However, I think we are missing the support for a guest using the > combination of PMEVTYPER.NS{K/U} instead of the PMEVTYPER.{P/U} for > filtering the events. As per Arm ARM, it is permitted to use the > PMEVTYPER.NSK/U (leaving PMEVTYPER.{P,U} == 0) for filtering in Non-Secure > EL1. Ah, good eye. The pseudocode is easy enough to rip off, something like the below diff would get things going. There's an extra step of making these bits RES0 if EL3 isn't present in the guest's ID register values, but not a huge deal. > Anyways, for this patch: > > Reviewed-by: Suzuki K Poulose idx); data = __vcpu_sys_reg(vcpu, reg); @@ -611,13 +612,18 @@ static void kvm_pmu_create_perf_event(struct kvm_pmc *pmc) !test_bit(eventsel, vcpu->kvm->arch.pmu_filter)) return; + p = data & ARMV8_PMU_EXCLUDE_EL1; + u = data & ARMV8_PMU_EXCLUDE_EL0; + nsk = data & ARMV8_PMU_EXCLUDE_NS_EL1; + nsu = data & ARMV8_PMU_EXCLUDE_NS_EL0; + memset(&attr, 0, sizeof(struct perf_event_attr)); attr.type = arm_pmu->pmu.type; attr.size = sizeof(attr); attr.pinned = 1; attr.disabled = !kvm_pmu_counter_is_enabled(pmc); - attr.exclude_user = data & ARMV8_PMU_EXCLUDE_EL0 ? 1 : 0; - attr.exclude_kernel = data & ARMV8_PMU_EXCLUDE_EL1 ? 1 : 0; + attr.exclude_user = (u != nsu); + attr.exclude_kernel = (p != nsk); attr.exclude_hv = 1; /* Don't count EL2 events */ attr.exclude_host = 1; /* Don't count host events */ attr.config = eventsel; @@ -663,7 +669,8 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data, if (!kvm_vcpu_has_pmu(vcpu)) return; - mask = ARMV8_PMU_EXCLUDE_EL1 | ARMV8_PMU_EXCLUDE_EL0; + mask = ARMV8_PMU_EXCLUDE_EL1 | ARMV8_PMU_EXCLUDE_EL0 | + ARMV8_PMU_EXCLUDE_NS_EL1 | ARMV8_PMU_EXCLUDE_NS_EL0; mask |= kvm_pmu_event_mask(vcpu->kvm); reg = counter_index_to_evtreg(pmc->idx); diff --git a/include/linux/perf/arm_pmuv3.h b/include/linux/perf/arm_pmuv3.h index 753f8dbd9d10..872119cc2bac 100644 --- a/include/linux/perf/arm_pmuv3.h +++ b/include/linux/perf/arm_pmuv3.h @@ -235,9 +235,11 @@ /* * Event filters for PMUv3 */ -#define ARMV8_PMU_EXCLUDE_EL1 (1U << 31) -#define ARMV8_PMU_EXCLUDE_EL0 (1U << 30) -#define ARMV8_PMU_INCLUDE_EL2 (1U << 27) +#define ARMV8_PMU_EXCLUDE_EL1 (1U << 31) +#define ARMV8_PMU_EXCLUDE_EL0 (1U << 30) +#define ARMV8_PMU_EXCLUDE_NS_EL1 (1U << 29) +#define ARMV8_PMU_EXCLUDE_NS_EL0 (1U << 28) +#define ARMV8_PMU_INCLUDE_EL2 (1U << 27) /* * PMUSERENR: user enable reg -- Best, Oliver