From: Leo Liang <ycliang@andestech.com>
To: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Cc: Rick Chen <rick@andestech.com>,
Sughosh Ganu <sughosh.ganu@linaro.org>,
Anup Patel <apatel@ventanamicro.com>,
Kautuk Consul <kconsul@ventanamicro.com>,
Chanho Park <chanho61.park@samsung.com>, <u-boot@lists.denx.de>
Subject: Re: [RFC v2 1/2] riscv: allow resume after exception
Date: Mon, 30 Oct 2023 16:24:22 +0800 [thread overview]
Message-ID: <ZT9oNj9AF_7ZopAE@swlinux02> (raw)
In-Reply-To: <20231029084533.44607-2-heinrich.schuchardt@canonical.com>
On Sun, Oct 29, 2023 at 09:45:32AM +0100, Heinrich Schuchardt wrote:
> If CSRs like seed are readable by S-mode, may not be determinable by
> S-mode. For safe driver probing allow to resume via a longjmp after an
> exception.
>
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> ---
> v2:
> new patch
> ---
> arch/riscv/lib/interrupts.c | 13 +++++++++++++
> include/interrupt.h | 22 ++++++++++++++++++++++
> 2 files changed, 35 insertions(+)
> create mode 100644 include/interrupt.h
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
next prev parent reply other threads:[~2023-10-30 8:28 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-29 8:45 [RFC v2 0/2] rng: Provide a RNG based on the RISC-V Zkr ISA extension Heinrich Schuchardt
2023-10-29 8:45 ` [RFC v2 1/2] riscv: allow resume after exception Heinrich Schuchardt
2023-10-30 8:24 ` Leo Liang [this message]
2023-10-31 7:53 ` Xiang W
2023-10-31 12:09 ` Heinrich Schuchardt
2023-10-31 15:19 ` Xiang W
2023-10-29 8:45 ` [RFC v2 2/2] rng: Provide a RNG based on the RISC-V Zkr ISA extension Heinrich Schuchardt
2023-10-30 8:25 ` Leo Liang
2023-10-31 6:16 ` merle w
2023-10-31 6:38 ` Heinrich Schuchardt
2023-10-31 6:43 ` Leo Liang
2023-10-31 7:55 ` Xiang W
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