From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Conor Dooley <conor@kernel.org>
Cc: <paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
<aou@eecs.berkeley.edu>, <linux-riscv@lists.infradead.org>,
<prabhakar.mahadev-lad.rj@bp.renesas.com>, <tim609@andestech.com>,
<dylan@andestech.com>, <locus84@andestech.com>,
<dminus@andestech.com>
Subject: Re: [PATCH v2 00/10] Support Andes PMU extension
Date: Fri, 20 Oct 2023 16:05:45 +0800 [thread overview]
Message-ID: <ZTI02VmswE5eR-_0@APC323> (raw)
In-Reply-To: <20231019-cargo-outright-1c0a34431626@spud>
On Thu, Oct 19, 2023 at 03:51:00PM +0100, Conor Dooley wrote:
> On Thu, Oct 19, 2023 at 09:52:38PM +0800, Yu Chien Peter Lin wrote:
> > Hi All,
> >
> > This patch series introduces the Andes PMU extension, which serves
> > the same purpose as Sscofpmf. In this version we use FDT-based
> > probing and the CONFIG_ANDES_CUSTOM_PMU to enable perf sampling
> > and filtering support.
> >
> > Its non-standard local interrupt is assigned to bit 18 in the
> > custom S-mode local interrupt pending CSR (slip), while the
> > interrupt cause is (256 + 18).
>
> Chief, you gotta thread your patchsets. It seems like every mail in this
> series has been sent individually, which is going to break tools like
> b4 and the automated testing on patchwork.
Hi Conor,
Sure, thanks for taking care of this!
Regards,
Peter Lin
> Cheers,
> Conor.
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prev parent reply other threads:[~2023-10-20 8:06 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-19 13:52 [PATCH v2 00/10] Support Andes PMU extension Yu Chien Peter Lin
2023-10-19 14:51 ` Conor Dooley
2023-10-20 8:05 ` Yu-Chien Peter Lin [this message]
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