From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-196.mta0.migadu.com (out-196.mta0.migadu.com [91.218.175.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 801091B283 for ; Tue, 24 Oct 2023 22:42:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="bbw/z89w" Date: Tue, 24 Oct 2023 22:41:57 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1698187321; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DSryayoirNu2u8X3Ok0uKcIUthQ11l2zHIdQh/RbHzM=; b=bbw/z89wfls1IcK9dYOBgLVNxd+FMt4F10IRWFJPvCngTrHMBMSfaKDzPXVugaunLmRyU5 5FlaEtakYXBhnEcmXgywprzOlS7r+eAgxg599saFUPh9IwDESSnz6Fo1tWtf15R/ro66al pu3nWBThftcKTHFYjqzv7yF9sXKVqyY= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Marc Zyngier Cc: Miguel Luis , "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Eric Auger , James Morse , Suzuki K Poulose , Zenghui Yu Subject: Re: [PATCH 5/5] KVM: arm64: Handle AArch32 SPSR_{irq,abt,und,fiq} as RAZ/WI Message-ID: References: <20231023095444.1587322-1-maz@kernel.org> <20231023095444.1587322-6-maz@kernel.org> <7DD05DC0-164E-440F-BEB1-E5040C512008@oracle.com> <86jzrc3pbm.wl-maz@kernel.org> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <86jzrc3pbm.wl-maz@kernel.org> X-Migadu-Flow: FLOW_OUT On Tue, Oct 24, 2023 at 06:25:33PM +0100, Marc Zyngier wrote: > On Mon, 23 Oct 2023 19:55:10 +0100, Miguel Luis wrote: > > Also, could you please explain what is happening at PSTATE.EL == EL1 > > and if EL2Enabled() && HCR_EL2.NV == ‘1’ ? > > We directly take the trap and not forward it. This isn't exactly the > letter of the architecture, but at the same time, treating these > registers as RAZ/WI is the only valid implementation. I don't > immediately see a problem with taking this shortcut. Ugh, that's annoying. The other EL2 views of AArch32 state UNDEF if EL1 doesn't implement AArch32. It'd be nice to get a relaxation in the architecture to allow an UNDEF here. Broadening the scope to KVM's emulation of AArch64-only behavior, I think we should be a bit more aggressive in sanitising AArch32 support from the ID registers. That way any AA64-only behavior in KVM is architectural from the guest POV. Maybe something like: diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 57c8190d5438..045f41900433 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1447,6 +1447,16 @@ static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, return REG_HIDDEN; } +#define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ +({ \ + u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ + (val) &= ~reg##_##field##_MASK; \ + (val) |= FIELD_PREP(reg##_##field##_MASK, \ + min(__f_val, (u64)reg##_##field##_##limit)); \ + (val); \ +}) + + static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { @@ -1477,19 +1487,38 @@ static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP); } + /* + * Hide AArch32 support if the vCPU wasn't configured for it. The + * architecture requires all higher ELs to be AArch64-only in this + * situation as well. + */ + if (!vcpu_el1_is_32bit(vcpu)) { + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64PFR0_EL1, EL1, IMP); + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64PFR0_EL1, EL2, IMP); + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64PFR0_EL1, EL3, IMP); + } + val &= ~ID_AA64PFR0_EL1_AMU_MASK; return val; } -#define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \ -({ \ - u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \ - (val) &= ~reg##_##field##_MASK; \ - (val) |= FIELD_PREP(reg##_##field##_MASK, \ - min(__f_val, (u64)reg##_##field##_##limit)); \ - (val); \ -}) +static u64 set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd, + u64 val) +{ + /* + * Older versions of KVM freely reported AArch32 support, even if the + * vCPU was configured for AArch64. + */ + if (!vcpu_el1_is_32bit(vcpu)) { + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64PFR0_EL1, EL1, IMP); + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64PFR0_EL1, EL2, IMP); + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64PFR0_EL1, EL3, IMP); + } + + return set_id_reg(vcpu, rd, val); +} static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) @@ -2055,7 +2084,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_ID_AA64PFR0_EL1), .access = access_id_reg, .get_user = get_id_reg, - .set_user = set_id_reg, + .set_user = set_id_aa64pfr0_el1, .reset = read_sanitised_id_aa64pfr0_el1, .val = ~(ID_AA64PFR0_EL1_AMU | ID_AA64PFR0_EL1_MPAM | -- Thanks, Oliver From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9112C25B47 for ; Tue, 24 Oct 2023 22:42:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0uz56KyiFjczKt3+d0sBLIEITaRUWKy8McfBWe/wzGQ=; b=4tgLB6jtukNzSu XE41bTYVu5nvUE6h03JCaA6vdpuz+niwFQdaqAMpqwyehYo+L1EqsvsYuXn8dc4BdrtYYws0678+f FTwZsads+vJoSLw7sc6k+ycQSTnw9seVCNExJ7DNgtZRXQCVMPlmDEAgNrlzzozM/ZcNkFPtQZSYE 053KkywBua5XNfdOOV+kOFoNrkc58zdZmEerdfkHFURkKTDTK5UNGlN9N5VsG+udCNNJ2YpL0NyIh pjk85ZzAV9JwOWlGCFj3YGHBhP/isqtrTjxs3fitEYcnT4KEJ2KWktjCQemo+a9C61kmdH+2sV6fA 2K8vttAPqgI4vKky6voA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qvQ6D-00Aysc-1t; Tue, 24 Oct 2023 22:42:09 +0000 Received: from out-209.mta0.migadu.com ([2001:41d0:1004:224b::d1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qvQ6A-00AyrT-18 for linux-arm-kernel@lists.infradead.org; Tue, 24 Oct 2023 22:42:08 +0000 Date: Tue, 24 Oct 2023 22:41:57 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1698187321; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DSryayoirNu2u8X3Ok0uKcIUthQ11l2zHIdQh/RbHzM=; b=bbw/z89wfls1IcK9dYOBgLVNxd+FMt4F10IRWFJPvCngTrHMBMSfaKDzPXVugaunLmRyU5 5FlaEtakYXBhnEcmXgywprzOlS7r+eAgxg599saFUPh9IwDESSnz6Fo1tWtf15R/ro66al pu3nWBThftcKTHFYjqzv7yF9sXKVqyY= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Marc Zyngier Cc: Miguel Luis , "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Eric Auger , James Morse , Suzuki K Poulose , Zenghui Yu Subject: Re: [PATCH 5/5] KVM: arm64: Handle AArch32 SPSR_{irq,abt,und,fiq} as RAZ/WI Message-ID: References: <20231023095444.1587322-1-maz@kernel.org> <20231023095444.1587322-6-maz@kernel.org> <7DD05DC0-164E-440F-BEB1-E5040C512008@oracle.com> <86jzrc3pbm.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <86jzrc3pbm.wl-maz@kernel.org> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231024_154206_820368_ADADC298 X-CRM114-Status: GOOD ( 18.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gVHVlLCBPY3QgMjQsIDIwMjMgYXQgMDY6MjU6MzNQTSArMDEwMCwgTWFyYyBaeW5naWVyIHdy b3RlOgo+IE9uIE1vbiwgMjMgT2N0IDIwMjMgMTk6NTU6MTAgKzAxMDAsIE1pZ3VlbCBMdWlzIDxt aWd1ZWwubHVpc0BvcmFjbGUuY29tPiB3cm90ZToKPiA+IEFsc28sIGNvdWxkIHlvdSBwbGVhc2Ug ZXhwbGFpbiB3aGF0IGlzIGhhcHBlbmluZyBhdCBQU1RBVEUuRUwgPT0gRUwxCj4gPiBhbmQgaWYg RUwyRW5hYmxlZCgpICYmIEhDUl9FTDIuTlYgPT0g4oCYMeKAmSAgPwo+IAo+IFdlIGRpcmVjdGx5 IHRha2UgdGhlIHRyYXAgYW5kIG5vdCBmb3J3YXJkIGl0LiBUaGlzIGlzbid0IGV4YWN0bHkgdGhl Cj4gbGV0dGVyIG9mIHRoZSBhcmNoaXRlY3R1cmUsIGJ1dCBhdCB0aGUgc2FtZSB0aW1lLCB0cmVh dGluZyB0aGVzZQo+IHJlZ2lzdGVycyBhcyBSQVovV0kgaXMgdGhlIG9ubHkgdmFsaWQgaW1wbGVt ZW50YXRpb24uIEkgZG9uJ3QKPiBpbW1lZGlhdGVseSBzZWUgYSBwcm9ibGVtIHdpdGggdGFraW5n IHRoaXMgc2hvcnRjdXQuCgpVZ2gsIHRoYXQncyBhbm5veWluZy4gVGhlIG90aGVyIEVMMiB2aWV3 cyBvZiBBQXJjaDMyIHN0YXRlIFVOREVGIGlmIEVMMQpkb2Vzbid0IGltcGxlbWVudCBBQXJjaDMy LiBJdCdkIGJlIG5pY2UgdG8gZ2V0IGEgcmVsYXhhdGlvbiBpbiB0aGUKYXJjaGl0ZWN0dXJlIHRv IGFsbG93IGFuIFVOREVGIGhlcmUuCgpCcm9hZGVuaW5nIHRoZSBzY29wZSB0byBLVk0ncyBlbXVs YXRpb24gb2YgQUFyY2g2NC1vbmx5IGJlaGF2aW9yLCBJCnRoaW5rIHdlIHNob3VsZCBiZSBhIGJp dCBtb3JlIGFnZ3Jlc3NpdmUgaW4gc2FuaXRpc2luZyBBQXJjaDMyIHN1cHBvcnQKZnJvbSB0aGUg SUQgcmVnaXN0ZXJzLiBUaGF0IHdheSBhbnkgQUE2NC1vbmx5IGJlaGF2aW9yIGluIEtWTSBpcwph cmNoaXRlY3R1cmFsIGZyb20gdGhlIGd1ZXN0IFBPVi4KCk1heWJlIHNvbWV0aGluZyBsaWtlOgoK ZGlmZiAtLWdpdCBhL2FyY2gvYXJtNjQva3ZtL3N5c19yZWdzLmMgYi9hcmNoL2FybTY0L2t2bS9z eXNfcmVncy5jCmluZGV4IDU3YzgxOTBkNTQzOC4uMDQ1ZjQxOTAwNDMzIDEwMDY0NAotLS0gYS9h cmNoL2FybTY0L2t2bS9zeXNfcmVncy5jCisrKyBiL2FyY2gvYXJtNjQva3ZtL3N5c19yZWdzLmMK QEAgLTE0NDcsNiArMTQ0NywxNiBAQCBzdGF0aWMgdW5zaWduZWQgaW50IHN2ZV92aXNpYmlsaXR5 KGNvbnN0IHN0cnVjdCBrdm1fdmNwdSAqdmNwdSwKIAlyZXR1cm4gUkVHX0hJRERFTjsKIH0KIAor I2RlZmluZSBJRF9SRUdfTElNSVRfRklFTERfRU5VTSh2YWwsIHJlZywgZmllbGQsIGxpbWl0KQkJ CVwKKyh7CQkJCQkJCQkJXAorCXU2NCBfX2ZfdmFsID0gRklFTERfR0VUKHJlZyMjXyMjZmllbGQj I19NQVNLLCB2YWwpOwkJXAorCSh2YWwpICY9IH5yZWcjI18jI2ZpZWxkIyNfTUFTSzsJCQkJCVwK KwkodmFsKSB8PSBGSUVMRF9QUkVQKHJlZyMjXyMjZmllbGQjI19NQVNLLAkJCVwKKwkJCW1pbihf X2ZfdmFsLCAodTY0KXJlZyMjXyMjZmllbGQjI18jI2xpbWl0KSk7CVwKKwkodmFsKTsJCQkJCQkJ CVwKK30pCisKKwogc3RhdGljIHU2NCByZWFkX3Nhbml0aXNlZF9pZF9hYTY0cGZyMF9lbDEoc3Ry dWN0IGt2bV92Y3B1ICp2Y3B1LAogCQkJCQkgIGNvbnN0IHN0cnVjdCBzeXNfcmVnX2Rlc2MgKnJk KQogewpAQCAtMTQ3NywxOSArMTQ4NywzOCBAQCBzdGF0aWMgdTY0IHJlYWRfc2FuaXRpc2VkX2lk X2FhNjRwZnIwX2VsMShzdHJ1Y3Qga3ZtX3ZjcHUgKnZjcHUsCiAJCXZhbCB8PSBTWVNfRklFTERf UFJFUF9FTlVNKElEX0FBNjRQRlIwX0VMMSwgR0lDLCBJTVApOwogCX0KIAorCS8qCisJICogSGlk ZSBBQXJjaDMyIHN1cHBvcnQgaWYgdGhlIHZDUFUgd2Fzbid0IGNvbmZpZ3VyZWQgZm9yIGl0LiBU aGUKKwkgKiBhcmNoaXRlY3R1cmUgcmVxdWlyZXMgYWxsIGhpZ2hlciBFTHMgdG8gYmUgQUFyY2g2 NC1vbmx5IGluIHRoaXMKKwkgKiBzaXR1YXRpb24gYXMgd2VsbC4KKwkgKi8KKwlpZiAoIXZjcHVf ZWwxX2lzXzMyYml0KHZjcHUpKSB7CisJCXZhbCA9IElEX1JFR19MSU1JVF9GSUVMRF9FTlVNKHZh bCwgSURfQUE2NFBGUjBfRUwxLCBFTDEsIElNUCk7CisJCXZhbCA9IElEX1JFR19MSU1JVF9GSUVM RF9FTlVNKHZhbCwgSURfQUE2NFBGUjBfRUwxLCBFTDIsIElNUCk7CisJCXZhbCA9IElEX1JFR19M SU1JVF9GSUVMRF9FTlVNKHZhbCwgSURfQUE2NFBGUjBfRUwxLCBFTDMsIElNUCk7CisJfQorCiAJ dmFsICY9IH5JRF9BQTY0UEZSMF9FTDFfQU1VX01BU0s7CiAKIAlyZXR1cm4gdmFsOwogfQogCi0j ZGVmaW5lIElEX1JFR19MSU1JVF9GSUVMRF9FTlVNKHZhbCwgcmVnLCBmaWVsZCwgbGltaXQpCQkJ ICAgICAgIFwKLSh7CQkJCQkJCQkJICAgICAgIFwKLQl1NjQgX19mX3ZhbCA9IEZJRUxEX0dFVChy ZWcjI18jI2ZpZWxkIyNfTUFTSywgdmFsKTsJCSAgICAgICBcCi0JKHZhbCkgJj0gfnJlZyMjXyMj ZmllbGQjI19NQVNLOwkJCQkJICAgICAgIFwKLQkodmFsKSB8PSBGSUVMRF9QUkVQKHJlZyMjXyMj ZmllbGQjI19NQVNLLAkJCSAgICAgICBcCi0JCQltaW4oX19mX3ZhbCwgKHU2NClyZWcjI18jI2Zp ZWxkIyNfIyNsaW1pdCkpOwkgICAgICAgXAotCSh2YWwpOwkJCQkJCQkJICAgICAgIFwKLX0pCitz dGF0aWMgdTY0IHNldF9pZF9hYTY0cGZyMF9lbDEoc3RydWN0IGt2bV92Y3B1ICp2Y3B1LAorCQkJ ICAgICAgIGNvbnN0IHN0cnVjdCBzeXNfcmVnX2Rlc2MgKnJkLAorCQkJICAgICAgIHU2NCB2YWwp Cit7CisJLyoKKwkgKiBPbGRlciB2ZXJzaW9ucyBvZiBLVk0gZnJlZWx5IHJlcG9ydGVkIEFBcmNo MzIgc3VwcG9ydCwgZXZlbiBpZiB0aGUKKwkgKiB2Q1BVIHdhcyBjb25maWd1cmVkIGZvciBBQXJj aDY0LgorCSAqLworCWlmICghdmNwdV9lbDFfaXNfMzJiaXQodmNwdSkpIHsKKwkJdmFsID0gSURf UkVHX0xJTUlUX0ZJRUxEX0VOVU0odmFsLCBJRF9BQTY0UEZSMF9FTDEsIEVMMSwgSU1QKTsKKwkJ dmFsID0gSURfUkVHX0xJTUlUX0ZJRUxEX0VOVU0odmFsLCBJRF9BQTY0UEZSMF9FTDEsIEVMMiwg SU1QKTsKKwkJdmFsID0gSURfUkVHX0xJTUlUX0ZJRUxEX0VOVU0odmFsLCBJRF9BQTY0UEZSMF9F TDEsIEVMMywgSU1QKTsKKwl9CisKKwlyZXR1cm4gc2V0X2lkX3JlZyh2Y3B1LCByZCwgdmFsKTsK K30KIAogc3RhdGljIHU2NCByZWFkX3Nhbml0aXNlZF9pZF9hYTY0ZGZyMF9lbDEoc3RydWN0IGt2 bV92Y3B1ICp2Y3B1LAogCQkJCQkgIGNvbnN0IHN0cnVjdCBzeXNfcmVnX2Rlc2MgKnJkKQpAQCAt MjA1NSw3ICsyMDg0LDcgQEAgc3RhdGljIGNvbnN0IHN0cnVjdCBzeXNfcmVnX2Rlc2Mgc3lzX3Jl Z19kZXNjc1tdID0gewogCXsgU1lTX0RFU0MoU1lTX0lEX0FBNjRQRlIwX0VMMSksCiAJICAuYWNj ZXNzID0gYWNjZXNzX2lkX3JlZywKIAkgIC5nZXRfdXNlciA9IGdldF9pZF9yZWcsCi0JICAuc2V0 X3VzZXIgPSBzZXRfaWRfcmVnLAorCSAgLnNldF91c2VyID0gc2V0X2lkX2FhNjRwZnIwX2VsMSwK IAkgIC5yZXNldCA9IHJlYWRfc2FuaXRpc2VkX2lkX2FhNjRwZnIwX2VsMSwKIAkgIC52YWwgPSB+ KElEX0FBNjRQRlIwX0VMMV9BTVUgfAogCQkgICBJRF9BQTY0UEZSMF9FTDFfTVBBTSB8CgotLSAK VGhhbmtzLApPbGl2ZXIKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fCmxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlz dHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3Rp bmZvL2xpbnV4LWFybS1rZXJuZWwK