From: Chao Gao <chao.gao@intel.com>
To: Jim Mattson <jmattson@google.com>
Cc: <kvm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
'Paolo Bonzini ' <pbonzini@redhat.com>,
'Sean Christopherson ' <seanjc@google.com>
Subject: Re: [PATCH 1/2] KVM: x86: Advertise CPUID.(EAX=7,ECX=2):EDX[5:0] to userspace
Date: Wed, 25 Oct 2023 15:06:49 +0800 [thread overview]
Message-ID: <ZTi+iTwNh28Amkp8@chao-email> (raw)
In-Reply-To: <20231024001636.890236-1-jmattson@google.com>
On Mon, Oct 23, 2023 at 05:16:35PM -0700, Jim Mattson wrote:
>The low five bits {INTEL_PSFD, IPRED_CTRL, RRSBA_CTRL, DDPD_U, BHI_CTRL}
>advertise the availability of specific bits in IA32_SPEC_CTRL. Since KVM
>dynamically determines the legal IA32_SPEC_CTRL bits for the underlying
>hardware, the hard work has already been done. Just let userspace know
>that a guest can use these IA32_SPEC_CTRL bits.
>
>The sixth bit (MCDT_NO) states that the processor does not exhibit MXCSR
>Configuration Dependent Timing (MCDT) behavior. This is an inherent
>property of the physical processor that is inherited by the virtual
>CPU. Pass that information on to userspace.
>
>Signed-off-by: Jim Mattson <jmattson@google.com>
Reviewed-by: Chao Gao <chao.gao@intel.com>
next prev parent reply other threads:[~2023-10-25 7:07 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-24 0:16 [PATCH 1/2] KVM: x86: Advertise CPUID.(EAX=7,ECX=2):EDX[5:0] to userspace Jim Mattson
2023-10-24 0:16 ` [PATCH 2/2] KVM: x86: Use a switch statement in __feature_translate() Jim Mattson
2023-10-24 0:25 ` Sean Christopherson
2023-11-30 20:28 ` Sean Christopherson
2023-12-01 1:39 ` Jim Mattson
2023-10-25 7:06 ` Chao Gao [this message]
2023-12-01 1:52 ` [PATCH 1/2] KVM: x86: Advertise CPUID.(EAX=7,ECX=2):EDX[5:0] to userspace Sean Christopherson
2023-12-01 4:18 ` Jim Mattson
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