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[99.254.144.39]) by smtp.gmail.com with ESMTPSA id pm10-20020ad446ca000000b0066d1f118b7esm4503683qvb.1.2023.10.25.08.14.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 08:14:44 -0700 (PDT) Date: Wed, 25 Oct 2023 11:14:42 -0400 From: Peter Xu To: Ethan Chen Cc: qemu-devel@nongnu.org, Paolo Bonzini , David Hildenbrand , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 2/6] system/physmem: IOMMU: Invoke the translate_size function if it is implemented Message-ID: References: <20231025051430.493079-1-ethan84@andestech.com> <20231025051430.493079-3-ethan84@andestech.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20231025051430.493079-3-ethan84@andestech.com> Received-SPF: pass client-ip=170.10.129.124; envelope-from=peterx@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Oct 25, 2023 at 01:14:26PM +0800, Ethan Chen wrote: > Signed-off-by: Ethan Chen > --- > system/physmem.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/system/physmem.c b/system/physmem.c > index fc2b0fee01..53b6ab735c 100644 > --- a/system/physmem.c > +++ b/system/physmem.c > @@ -432,8 +432,13 @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm > iommu_idx = imrc->attrs_to_index(iommu_mr, attrs); > } > > - iotlb = imrc->translate(iommu_mr, addr, is_write ? > - IOMMU_WO : IOMMU_RO, iommu_idx); > + if (imrc->translate_size) { > + iotlb = imrc->translate_size(iommu_mr, addr, *plen_out, is_write ? > + IOMMU_WO : IOMMU_RO, iommu_idx); > + } else { > + iotlb = imrc->translate(iommu_mr, addr, is_write ? > + IOMMU_WO : IOMMU_RO, iommu_idx); > + } Currently the translation size is encoded in iotlb.addr_mask. Can riscv do the same? For example, lookup addr in match_entry_md() ranges, report size back into iotlb.addr_mask, rather than enforcing *plen_out range always resides in one translation only. IMHO it's actually legal if *plen_out covers more than one IOMMU translations. QEMU memory core should have taken care of that by separately translate the ranges and apply RW on top. With current proposal of translate_size() I think it'll fail instead, which is not wanted. Thanks, -- Peter Xu