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[99.254.144.39]) by smtp.gmail.com with ESMTPSA id l10-20020ac848ca000000b004108d49f391sm5027195qtr.48.2023.10.26.07.20.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Oct 2023 07:20:42 -0700 (PDT) Date: Thu, 26 Oct 2023 10:20:41 -0400 From: Peter Xu To: Ethan Chen Cc: qemu-devel@nongnu.org, Paolo Bonzini , David Hildenbrand , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: [PATCH 2/6] system/physmem: IOMMU: Invoke the translate_size function if it is implemented Message-ID: References: <20231025051430.493079-1-ethan84@andestech.com> <20231025051430.493079-3-ethan84@andestech.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=170.10.133.124; envelope-from=peterx@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Oct 26, 2023 at 02:48:14PM +0800, Ethan Chen wrote: > My target is to support IOPMP partially hit error. IOPMP checks whole memory > access region is in the same entry. If not, reject the access instead of modify > the access size. Could you elaborate why is that important? In what use case? Consider IOVA mapped for address range iova=[0, 4K] only, here we have a DMA request with range=[0, 8K]. Now my understanding is what you want to achieve is don't trigger the DMA to [0, 4K] and fail the whole [0, 8K] request. Can we just fail at the latter DMA [4K, 8K] when it happens? After all, IIUC a device can split the 0-8K DMA into two smaller DMAs, then the 1st chunk can succeed then if it falls in 0-4K. Some further explanation of the failure use case could be helpful. Thanks, -- Peter Xu