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From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Stewart Hildebrand <stewart.hildebrand@amd.com>
Cc: xen-devel@lists.xenproject.org,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	George Dunlap <george.dunlap@citrix.com>,
	Jan Beulich <jbeulich@suse.com>, Julien Grall <julien@xen.org>,
	Stefano Stabellini <sstabellini@kernel.org>, Wei Liu <wl@xen.org>
Subject: Re: [PATCH v7 1/2] xen/vpci: header: status register handler
Date: Thu, 23 Nov 2023 09:14:36 +0100	[thread overview]
Message-ID: <ZV8J7CoFJyN9a5GO@macbook> (raw)
In-Reply-To: <a28239cd-e94e-4e0e-b415-a7ae32befd40@amd.com>

On Wed, Nov 22, 2023 at 03:16:29PM -0500, Stewart Hildebrand wrote:
> On 11/17/23 07:40, Roger Pau Monné wrote:
> > On Wed, Sep 13, 2023 at 10:35:46AM -0400, Stewart Hildebrand wrote:
> >>      r->write(pdev, r->offset, data & (0xffffffffU >> (32 - 8 * r->size)),
> >>               r->private);
> >>  }
> >> diff --git a/xen/include/xen/pci_regs.h b/xen/include/xen/pci_regs.h
> >> index 84b18736a85d..b72131729db6 100644
> >> --- a/xen/include/xen/pci_regs.h
> >> +++ b/xen/include/xen/pci_regs.h
> >> @@ -66,6 +66,15 @@
> >>  #define  PCI_STATUS_REC_MASTER_ABORT	0x2000 /* Set on master abort */
> >>  #define  PCI_STATUS_SIG_SYSTEM_ERROR	0x4000 /* Set when we drive SERR */
> >>  #define  PCI_STATUS_DETECTED_PARITY	0x8000 /* Set on parity error */
> >> +#define  PCI_STATUS_RSVDZ_MASK		0x0006
> > 
> > In my copy of the PCIe 6 spec bit 6 is also RsvdZ, so the mask should
> > be 0x46.
> 
> Right, mine too. It's probably safer to follow the newer version of the spec, so I'll make the change. For completeness / archaeology purposes, I just want to document some relevant data points here.
> 
> In PCIe 4 spec, it says this about bit 6:
> "These bits were used in previous versions of the programming model. Careful consideration should be given to any attempt to repurpose them."
> 
> Going further back, PCI (old school PCI, not Express) spec 3.0 says this about bit 6:
> "This bit is reserved. *"
> "* In Revision 2.1 of this specification, this bit was used to indicate whether or not a device supported User Definable Features."
> 
> Just above in our pci_regs.h (and equally in Linux include/uapi/linux/pci_regs.h) we have this definition for bit 6:
> #define  PCI_STATUS_UDF         0x40    /* Support User Definable Features [obsolete] */
> 
> Qemu hw/xen/xen_pt_config_init.c treats bit 6 as RO:
>         .ro_mask    = 0x06F8,

Right, given the implementation of ro_mask that would likely be fine.
Reading unconditionally as 0 while preserving the value on writes
seems the safest option.

Thanks, Roger.


  reply	other threads:[~2023-11-23  8:14 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-13 14:35 [PATCH v7 0/2] vPCI capabilities filtering Stewart Hildebrand
2023-09-13 14:35 ` [PATCH v7 1/2] xen/vpci: header: status register handler Stewart Hildebrand
2023-09-14 11:12   ` Jan Beulich
2023-11-17 12:40   ` Roger Pau Monné
2023-11-17 13:23     ` Jan Beulich
2023-11-17 13:45       ` Roger Pau Monné
2023-11-17 16:45     ` Roger Pau Monné
2023-11-22 20:16     ` Stewart Hildebrand
2023-11-23  8:14       ` Roger Pau Monné [this message]
2023-11-23 12:57         ` Stewart Hildebrand
2023-11-23 14:21           ` Roger Pau Monné
2023-11-17 13:33   ` Roger Pau Monné
2023-11-22 22:04     ` Stewart Hildebrand
2023-11-21 14:45   ` Roger Pau Monné
2023-11-21 15:03     ` Stewart Hildebrand
2023-11-21 15:18       ` Roger Pau Monné
2023-11-21 16:27         ` Stewart Hildebrand
2023-11-21 16:46           ` Stewart Hildebrand
2023-09-13 14:35 ` [PATCH v7 2/2] xen/vpci: header: filter PCI capabilities Stewart Hildebrand
2023-11-17 11:44   ` Roger Pau Monné
2023-11-28 16:04     ` Stewart Hildebrand

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