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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 3/4] drm/i915: convert vlv_dpio_read()/write() from pipe to phy
Date: Tue, 14 Nov 2023 11:13:55 +0200	[thread overview]
Message-ID: <ZVM6UwJOeOU_9Pdl@intel.com> (raw)
In-Reply-To: <20231113164711.4100548-3-jani.nikula@intel.com>

On Mon, Nov 13, 2023 at 06:47:10PM +0200, Jani Nikula wrote:
> vlv_dpio_read() and vlv_dpio_write() really operate on the phy, not
> pipe. Passing the pipe instead of the phy as parameter is supposed to be
> a convenience, but when the caller has the phy, it becomes an
> inconvenience. See e.g. chv_dpio_cmn_power_well_enable() and
> assert_chv_phy_powergate().
> 
> Figure out the phy in the callers, and pass phy to the dpio functions.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  .../i915/display/intel_display_power_well.c   |  23 +--
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c | 160 +++++++++---------
>  drivers/gpu/drm/i915/display/intel_dpll.c     | 106 ++++++------
>  drivers/gpu/drm/i915/vlv_sideband.c           |  10 +-
>  drivers/gpu/drm/i915/vlv_sideband.h           |   6 +-
>  5 files changed, 152 insertions(+), 153 deletions(-)
<snip>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index d6af46e33424..32886c0ec2cc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -1107,24 +1109,24 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
> -	enum pipe pipe = crtc->pipe;
> +	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>  	u32 val;
>  
>  	vlv_dpio_get(dev_priv);
>  
>  	/* Enable clock channels for this port */
> -	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
> +	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(port));
>  	val = 0;
> -	if (pipe)
> +	if (phy)

That is wrong. Apart from that looks identical to what I have in
one of my branches :)

With that bogus change dropped:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2023-11-14  9:14 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-13 16:47 [Intel-gfx] [PATCH 1/4] drm/i915: move *_crtc_clock_get() to intel_dpll.c Jani Nikula
2023-11-13 16:47 ` [Intel-gfx] [PATCH 2/4] drm/i915: add vlv_pipe_to_phy() helper to replace DPIO_PHY() Jani Nikula
2023-11-14  9:04   ` Ville Syrjälä
2023-11-13 16:47 ` [Intel-gfx] [PATCH 3/4] drm/i915: convert vlv_dpio_read()/write() from pipe to phy Jani Nikula
2023-11-14  9:13   ` Ville Syrjälä [this message]
2023-11-14 10:26     ` Jani Nikula
2023-11-13 16:47 ` [Intel-gfx] [PATCH 4/4] drm/i915: move sideband regs to vlv_sideband_reg.h Jani Nikula
2023-11-14  9:19   ` Ville Syrjälä
2023-11-14 10:29     ` Jani Nikula
2023-11-13 21:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: move *_crtc_clock_get() to intel_dpll.c Patchwork
2023-11-13 21:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-11-13 22:16 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-11-14  9:02 ` [Intel-gfx] [PATCH 1/4] " Ville Syrjälä
2023-11-14 15:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915: move *_crtc_clock_get() to intel_dpll.c (rev2) Patchwork
2023-11-14 15:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-11-14 15:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-11-16  0:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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