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From: Jisheng Zhang <jszhang@kernel.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>, Chao Wei <chao.wei@sophgo.com>,
	Chen Wang <unicorn_wang@outlook.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH 1/4] dt-bindings: reset: Add binding for Sophgo CV1800B reset controller
Date: Wed, 15 Nov 2023 21:27:14 +0800	[thread overview]
Message-ID: <ZVTHMsXaPdHiuUOF@xhacker> (raw)
In-Reply-To: <44f21244-5bf1-4e0f-80a9-6ec76d65eea4@linaro.org>

On Tue, Nov 14, 2023 at 10:12:35PM +0100, Krzysztof Kozlowski wrote:
> On 13/11/2023 01:55, Jisheng Zhang wrote:
> ...
> 
> > diff --git a/include/dt-bindings/reset/sophgo,cv1800b-reset.h b/include/dt-bindings/reset/sophgo,cv1800b-reset.h
> > new file mode 100644
> > index 000000000000..28dda71369b4
> > --- /dev/null
> > +++ b/include/dt-bindings/reset/sophgo,cv1800b-reset.h
> > @@ -0,0 +1,96 @@
> > +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
> > +/*
> > + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
> > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> > + */
> > +
> > +#ifndef _DT_BINDINGS_CV1800B_RESET_H
> > +#define _DT_BINDINGS_CV1800B_RESET_H
> > +
> > +/*				0-1	*/
> > +#define RST_DDR			2
> > +#define RST_H264C		3
> > +#define RST_JPEG		4
> > +#define RST_H265C		5
> > +#define RST_VIPSYS		6
> > +#define RST_TDMA		7
> > +#define RST_TPU			8
> > +#define RST_TPUSYS		9
> > +/*				10	*/
> 
> Why do you have empty IDs? IDs start at 0 and are incremented by 1.

there's 1:1 mapping between the ID and bit. Some bits are reserved, I.E
no actions at all. Is "ID start at 0 and increment by 1" documented
in some docs? From another side, I also notice some SoCs especially
those which make use of reset-simple driver don't strictly follow
this rule, for example, amlogic,meson-a1-reset.h and so on. What
happened?

And I'd like to ask a question here before cooking 2nd version:
if the HW programming logic is the same as reset-simple, but some
or many bits are reserved, what's the can-be-accepted way to support
the reset controller? Use reset-simple? Obviously if we want the
"ID start at 0 and increment by 1" rule, then we have to write
a custom driver which almost use the reset-simple but with a
customized mapping.

Thanks

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>, Chao Wei <chao.wei@sophgo.com>,
	Chen Wang <unicorn_wang@outlook.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH 1/4] dt-bindings: reset: Add binding for Sophgo CV1800B reset controller
Date: Wed, 15 Nov 2023 21:27:14 +0800	[thread overview]
Message-ID: <ZVTHMsXaPdHiuUOF@xhacker> (raw)
In-Reply-To: <44f21244-5bf1-4e0f-80a9-6ec76d65eea4@linaro.org>

On Tue, Nov 14, 2023 at 10:12:35PM +0100, Krzysztof Kozlowski wrote:
> On 13/11/2023 01:55, Jisheng Zhang wrote:
> ...
> 
> > diff --git a/include/dt-bindings/reset/sophgo,cv1800b-reset.h b/include/dt-bindings/reset/sophgo,cv1800b-reset.h
> > new file mode 100644
> > index 000000000000..28dda71369b4
> > --- /dev/null
> > +++ b/include/dt-bindings/reset/sophgo,cv1800b-reset.h
> > @@ -0,0 +1,96 @@
> > +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
> > +/*
> > + * Copyright (C) 2023 Sophgo Technology Inc. All rights reserved.
> > + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> > + */
> > +
> > +#ifndef _DT_BINDINGS_CV1800B_RESET_H
> > +#define _DT_BINDINGS_CV1800B_RESET_H
> > +
> > +/*				0-1	*/
> > +#define RST_DDR			2
> > +#define RST_H264C		3
> > +#define RST_JPEG		4
> > +#define RST_H265C		5
> > +#define RST_VIPSYS		6
> > +#define RST_TDMA		7
> > +#define RST_TPU			8
> > +#define RST_TPUSYS		9
> > +/*				10	*/
> 
> Why do you have empty IDs? IDs start at 0 and are incremented by 1.

there's 1:1 mapping between the ID and bit. Some bits are reserved, I.E
no actions at all. Is "ID start at 0 and increment by 1" documented
in some docs? From another side, I also notice some SoCs especially
those which make use of reset-simple driver don't strictly follow
this rule, for example, amlogic,meson-a1-reset.h and so on. What
happened?

And I'd like to ask a question here before cooking 2nd version:
if the HW programming logic is the same as reset-simple, but some
or many bits are reserved, what's the can-be-accepted way to support
the reset controller? Use reset-simple? Obviously if we want the
"ID start at 0 and increment by 1" rule, then we have to write
a custom driver which almost use the reset-simple but with a
customized mapping.

Thanks

  reply	other threads:[~2023-11-15 13:39 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-13  0:54 [PATCH 0/4] riscv: sophgo: add reset support for cv1800b Jisheng Zhang
2023-11-13  0:54 ` Jisheng Zhang
2023-11-13  0:55 ` [PATCH 1/4] dt-bindings: reset: Add binding for Sophgo CV1800B reset controller Jisheng Zhang
2023-11-13  0:55   ` Jisheng Zhang
2023-11-13 13:36   ` Conor Dooley
2023-11-13 13:36     ` Conor Dooley
2023-11-13 14:00     ` Jisheng Zhang
2023-11-13 14:00       ` Jisheng Zhang
2023-11-14 21:13       ` Krzysztof Kozlowski
2023-11-14 21:13         ` Krzysztof Kozlowski
2023-11-14 21:12   ` Krzysztof Kozlowski
2023-11-14 21:12     ` Krzysztof Kozlowski
2023-11-15 13:27     ` Jisheng Zhang [this message]
2023-11-15 13:27       ` Jisheng Zhang
2023-11-15 14:56       ` Samuel Holland
2023-11-15 14:56         ` Samuel Holland
2023-11-15 15:02         ` Conor Dooley
2023-11-15 15:02           ` Conor Dooley
2023-11-15 15:15           ` Jisheng Zhang
2023-11-15 15:15             ` Jisheng Zhang
2023-11-15 21:00             ` Krzysztof Kozlowski
2023-11-15 21:00               ` Krzysztof Kozlowski
2023-11-13  0:55 ` [PATCH 2/4] reset: Add reset controller support for Sophgo CV1800B SoC Jisheng Zhang
2023-11-13  0:55   ` Jisheng Zhang
2023-11-13  0:55 ` [PATCH 3/4] riscv: dts: sophgo: add reset dt node for cv1800b Jisheng Zhang
2023-11-13  0:55   ` Jisheng Zhang
2023-11-13 14:32   ` Yixun Lan
2023-11-13 14:32     ` Yixun Lan
2023-11-13 15:14     ` Jisheng Zhang
2023-11-13 15:14       ` Jisheng Zhang
2023-11-13 15:37       ` Samuel Holland
2023-11-13 15:37         ` Samuel Holland
2023-11-14 14:55         ` Jisheng Zhang
2023-11-14 14:55           ` Jisheng Zhang
2023-11-13  0:55 ` [PATCH 4/4] riscv: dts: sophgo: add reset phandle to all uart nodes Jisheng Zhang
2023-11-13  0:55   ` Jisheng Zhang
2023-11-13  2:04   ` Samuel Holland
2023-11-13  2:04     ` Samuel Holland
2023-11-13 13:09     ` Jisheng Zhang
2023-11-13 13:09       ` Jisheng Zhang
2023-11-13  4:57   ` kernel test robot
2023-11-13  4:57     ` kernel test robot

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