From: Matthew Brost <matthew.brost@intel.com>
To: "Michał Winiarski" <michal.winiarski@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>,
intel-xe@lists.freedesktop.org
Subject: Re: [Intel-xe] [PATCH v3 20/20] drm/xe: Initialize GuC earlier during probe
Date: Wed, 15 Nov 2023 15:09:31 +0000 [thread overview]
Message-ID: <ZVTfK2Z3xUND4DZA@DUT025-TGLU.fm.intel.com> (raw)
In-Reply-To: <20231114130231.2299661-21-michal.winiarski@intel.com>
On Tue, Nov 14, 2023 at 02:02:31PM +0100, Michał Winiarski wrote:
> SR-IOV VF has limited access to MMIO registers. Fortunately, it is able
> to access a curated subset that is needed to initialize the driver by
> communicating with SR-IOV PF using GuC CT.
> Initialize GuC earlier in order to keep the unified probe ordering
> between VF and PF modes.
>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> ---
> drivers/gpu/drm/xe/xe_device.c | 11 +++++++++++
> drivers/gpu/drm/xe/xe_gt.c | 16 ++++------------
> drivers/gpu/drm/xe/xe_guc.c | 15 ++++++++++-----
> drivers/gpu/drm/xe/xe_uc.c | 35 ++++++++++++++++++++++++++--------
> 4 files changed, 52 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index 531aca74e8eb4..ecbf1effecc41 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -32,6 +32,7 @@
> #include "xe_pat.h"
> #include "xe_pcode.h"
> #include "xe_pm.h"
> +#include "xe_uc.h"
> #include "xe_query.h"
> #include "xe_tile.h"
> #include "xe_ttm_stolen_mgr.h"
> @@ -414,6 +415,16 @@ int xe_device_probe(struct xe_device *xe)
> return err;
> }
>
> + for_each_gt(gt, xe, id) {
> + err = xe_uc_init(>->uc);
> + if (err)
> + return err;
> +
> + err = xe_uc_init_hwconfig(>->uc);
> + if (err)
> + return err;
> + }
> +
I think this should be a GT level function rather touching the UC layer
here. Also maybe combine xe_force_wake_init_gt & xe_ggtt_init_early into
this new function too if it makes sense.
Also a comment of why this located wouldn't hurt either.
Other than these nits the patch itslef makes sense to me.
Matt
> err = drmm_add_action_or_reset(&xe->drm, xe_driver_flr_fini, xe);
> if (err)
> return err;
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index 73665e4e66f22..bee661e1f164a 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -344,14 +344,6 @@ static int gt_fw_domain_init(struct xe_gt *gt)
> goto err_force_wake;
> }
>
> - err = xe_uc_init(>->uc);
> - if (err)
> - goto err_force_wake;
> -
> - err = xe_uc_init_hwconfig(>->uc);
> - if (err)
> - goto err_force_wake;
> -
> xe_gt_idle_sysfs_init(>->gtidle);
>
> /* XXX: Fake that we pull the engine mask from hwconfig blob */
> @@ -415,10 +407,6 @@ static int all_fw_domain_init(struct xe_gt *gt)
> if (err)
> goto err_force_wake;
>
> - err = xe_uc_init_post_hwconfig(>->uc);
> - if (err)
> - goto err_force_wake;
> -
> if (!xe_gt_is_media_type(gt)) {
> /*
> * USM has its only SA pool to non-block behind user operations
> @@ -442,6 +430,10 @@ static int all_fw_domain_init(struct xe_gt *gt)
> }
> }
>
> + err = xe_uc_init_post_hwconfig(>->uc);
> + if (err)
> + goto err_force_wake;
> +
> err = xe_uc_init_hw(>->uc);
> if (err)
> goto err_force_wake;
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index e04b04be32b7d..895bcc24ae2c8 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -572,26 +572,31 @@ static int __xe_guc_upload(struct xe_guc *guc)
> */
> int xe_guc_min_load_for_hwconfig(struct xe_guc *guc)
> {
> + struct xe_gt *gt = guc_to_gt(guc);
> int ret;
>
> xe_guc_ads_populate_minimal(&guc->ads);
>
> + ret = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
> + if (ret)
> + return ret;
> +
> /* Raise GT freq to speed up HuC/GuC load */
> xe_guc_pc_init_early(&guc->pc);
>
> ret = __xe_guc_upload(guc);
> if (ret)
> - return ret;
> + goto out;
>
> ret = xe_guc_hwconfig_init(guc);
> if (ret)
> - return ret;
> + goto out;
>
> ret = xe_guc_enable_communication(guc);
> - if (ret)
> - return ret;
> +out:
> + xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
>
> - return 0;
> + return ret;
> }
>
> int xe_guc_upload(struct xe_guc *guc)
> diff --git a/drivers/gpu/drm/xe/xe_uc.c b/drivers/gpu/drm/xe/xe_uc.c
> index 13e76e6805ca1..069207a7f2f21 100644
> --- a/drivers/gpu/drm/xe/xe_uc.c
> +++ b/drivers/gpu/drm/xe/xe_uc.c
> @@ -29,8 +29,16 @@ uc_to_xe(struct xe_uc *uc)
> /* Should be called once at driver load only */
> int xe_uc_init(struct xe_uc *uc)
> {
> + struct xe_device *xe = uc_to_xe(uc);
> + struct xe_gt *gt = uc_to_gt(uc);
> int ret;
>
> + xe_device_mem_access_get(xe);
> +
> + ret = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT);
> + if (ret)
> + goto err;
> +
> /*
> * We call the GuC/HuC init functions even if GuC submission is off to
> * correctly move our tracking of the FW state to "disabled".
> @@ -38,26 +46,36 @@ int xe_uc_init(struct xe_uc *uc)
>
> ret = xe_guc_init(&uc->guc);
> if (ret)
> - goto err;
> + goto err_fw;
>
> ret = xe_huc_init(&uc->huc);
> if (ret)
> - goto err;
> + goto err_fw;
>
> if (!xe_device_uc_enabled(uc_to_xe(uc)))
> - return 0;
> + goto out;
> +
>
> ret = xe_wopcm_init(&uc->wopcm);
> if (ret)
> - goto err;
> + goto err_fw;
>
> ret = xe_guc_submit_init(&uc->guc);
> if (ret)
> - goto err;
> + goto err_fw;
> +
> +out:
> + xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
> +
> + xe_device_mem_access_put(xe);
>
> return 0;
>
> +err_fw:
> + xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
> err:
> + xe_device_mem_access_put(xe);
> +
> return ret;
> }
>
> @@ -117,17 +135,18 @@ int xe_uc_sanitize_reset(struct xe_uc *uc)
> */
> int xe_uc_init_hwconfig(struct xe_uc *uc)
> {
> + struct xe_device *xe = uc_to_xe(uc);
> int ret;
>
> /* GuC submission not enabled, nothing to do */
> if (!xe_device_uc_enabled(uc_to_xe(uc)))
> return 0;
>
> + xe_device_mem_access_get(xe);
> ret = xe_guc_min_load_for_hwconfig(&uc->guc);
> - if (ret)
> - return ret;
> + xe_device_mem_access_put(xe);
>
> - return 0;
> + return ret;
> }
>
> /*
> --
> 2.42.1
>
next prev parent reply other threads:[~2023-11-15 22:11 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-14 13:02 [Intel-xe] [PATCH v3 00/20] drm/xe: Probe tweaks and reordering Michał Winiarski
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 01/20] drm/xe: Skip calling drm_dev_put on probe error Michał Winiarski
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 02/20] drm/xe: Use managed pci_enable_device Michał Winiarski
2023-11-15 20:47 ` Matt Roper
2023-11-21 12:45 ` Michał Winiarski
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 03/20] drm/xe/irq: Don't call pci_free_irq_vectors Michał Winiarski
2023-11-15 20:49 ` Matt Roper
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 04/20] drm/xe: Move xe_set_dma_info outside of MMIO setup Michał Winiarski
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 05/20] drm/xe: Move xe_mmio_probe_tiles " Michał Winiarski
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 06/20] drm/xe: Split xe_info_init Michał Winiarski
2023-11-20 19:47 ` Lucas De Marchi
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 07/20] drm/xe: Introduce xe_tile_init_early and use at earlier point in probe Michał Winiarski
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 08/20] drm/xe: Map the entire BAR0 and hold onto the initial mapping Michał Winiarski
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 09/20] drm/xe/device: Introduce xe_device_probe_early Michał Winiarski
2023-11-15 14:41 ` Matthew Brost
2023-11-15 21:31 ` Matt Roper
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 10/20] drm/xe: Don't "peek" into GMD_ID Michał Winiarski
2023-11-15 14:45 ` Matthew Brost
2023-11-15 21:51 ` Matt Roper
2023-11-20 19:57 ` Lucas De Marchi
2023-11-21 13:27 ` Michał Winiarski
2023-11-21 16:54 ` Lucas De Marchi
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 11/20] drm/xe: Move system memory management init to earlier point in probe Michał Winiarski
2023-11-15 21:55 ` Matt Roper
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 12/20] drm/xe: Move force_wake " Michał Winiarski
2023-11-15 21:59 ` Matt Roper
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 13/20] drm/xe: Reorder GGTT " Michał Winiarski
2023-11-15 22:19 ` Matt Roper
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 14/20] drm/xe/uc: Split xe_uc_fw_init Michał Winiarski
2023-11-15 22:28 ` Matt Roper
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 15/20] drm/xe/uc: Store firmware binary in system-memory backed BO Michał Winiarski
2023-11-15 22:34 ` Matt Roper
2023-11-20 20:04 ` Lucas De Marchi
2023-11-20 21:34 ` Daniele Ceraolo Spurio
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 16/20] drm/xe/uc: Extract xe_uc_sanitize_reset Michał Winiarski
2023-11-16 12:56 ` Matthew Brost
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 17/20] drm/xe/guc: Split GuC params used for "hwconfig" and "post-hwconfig" Michał Winiarski
2023-11-20 13:25 ` Matthew Brost
2023-11-20 20:09 ` Lucas De Marchi
2023-11-21 13:36 ` Michał Winiarski
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 18/20] drm/xe/guc: Allocate GuC data structures in system memory for initial load Michał Winiarski
2023-11-20 20:20 ` Lucas De Marchi
2023-11-21 13:42 ` Michał Winiarski
2023-11-21 16:49 ` Lucas De Marchi
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 19/20] drm/xe/guc: Move GuC power control init to "post-hwconfig" Michał Winiarski
2023-11-20 13:30 ` Matthew Brost
2023-11-14 13:02 ` [Intel-xe] [PATCH v3 20/20] drm/xe: Initialize GuC earlier during probe Michał Winiarski
2023-11-15 15:09 ` Matthew Brost [this message]
2023-11-21 16:07 ` Michał Winiarski
2023-11-14 13:07 ` [Intel-xe] ✓ CI.Patch_applied: success for drm/xe: Probe tweaks and reordering (rev2) Patchwork
2023-11-14 13:08 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-11-14 13:09 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-11-14 13:16 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-11-14 13:16 ` [Intel-xe] ✓ CI.Hooks: " Patchwork
2023-11-14 13:18 ` [Intel-xe] ✓ CI.checksparse: " Patchwork
2023-11-14 13:51 ` [Intel-xe] ✓ CI.BAT: " Patchwork
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