From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DEADCC072A2 for ; Fri, 17 Nov 2023 16:46:13 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.635320.991209 (Exim 4.92) (envelope-from ) id 1r41ye-0002IV-Li; Fri, 17 Nov 2023 16:45:56 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 635320.991209; Fri, 17 Nov 2023 16:45:56 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r41ye-0002IO-J4; Fri, 17 Nov 2023 16:45:56 +0000 Received: by outflank-mailman (input) for mailman id 635320; Fri, 17 Nov 2023 16:45:54 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1r41yc-0002II-OZ for xen-devel@lists.xenproject.org; Fri, 17 Nov 2023 16:45:54 +0000 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [2a00:1450:4864:20::335]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id c529c0b9-8568-11ee-9b0e-b553b5be7939; Fri, 17 Nov 2023 17:45:52 +0100 (CET) Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-4079ed65582so17168565e9.1 for ; Fri, 17 Nov 2023 08:45:52 -0800 (PST) Received: from localhost ([213.195.113.99]) by smtp.gmail.com with ESMTPSA id p19-20020a05600c05d300b004081a011c0esm7523360wmd.12.2023.11.17.08.45.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Nov 2023 08:45:51 -0800 (PST) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: c529c0b9-8568-11ee-9b0e-b553b5be7939 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=citrix.com; s=google; t=1700239552; x=1700844352; darn=lists.xenproject.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=yVo6DqtPUzrFKz0gl1yax1yTDGlE+9FdDqEQaRRgmYo=; b=M9WAnZ2hzXBU2ooLPiiuLIA2y62CvnaD7ASAHfrPGf3MMlX3cj5OQXli9DDaig0U+d atigqkSa4nfSFNAsWJkPbymw8f2SQIXD+wUk3wCM9xhaBo2d7wER1XvtWn1n3LyoK0rt fwzRO6sIbgPgTSEP9UYgZx/sqhJWTPy5zT1GQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700239552; x=1700844352; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=yVo6DqtPUzrFKz0gl1yax1yTDGlE+9FdDqEQaRRgmYo=; b=Lsah+33Z/JgvCjPm4G6m9HjaDtqoQlrBQgbGcOQdnNRlERbXwHLsaAdUfO4KE9s1Iw 67sI55FfIwvEJIUzYV4HLEWtTUKHl0mhCbOM07iBz8jGvbd+GtRqntpDiIUjSwX0jfZa sgTyMCZbRgIWb13+MtWTG1KBB5w5YumTgwubPdd0DdTCVX8+KCSNmid4henllBluSdG/ /naTh9VRaLj+SGlsfEYE3Z/X28m/w4JCTe/VCiUeRRb1stKYJeDmEEay00WyPCBUwUfH Seo0u6r6avekE3Fh4+IcdpaV/WIpZce9GlU6dX/OotrP0R+Pb5/QE+jKkTqPkGeCbL42 0Zpw== X-Gm-Message-State: AOJu0Ywr4pkZN/QTfPg//6qA0AtkKSyFQn/qZV5tzAQYfg2KTiMjnZLB O0xFB6RJ1gxO/Gxk5nmvl17S7zV9z1YTUVqvnKE= X-Google-Smtp-Source: AGHT+IGnG6iTsOCEeWm1J9/vBV8FvHt1UXZ8jhBsSjIYIOIg9UodqxSKA+w49PcJtZA/V+3cAN5uWQ== X-Received: by 2002:a05:600c:3c87:b0:402:8896:bb7b with SMTP id bg7-20020a05600c3c8700b004028896bb7bmr14473294wmb.6.1700239552120; Fri, 17 Nov 2023 08:45:52 -0800 (PST) Date: Fri, 17 Nov 2023 17:45:50 +0100 From: Roger Pau =?utf-8?B?TW9ubsOp?= To: Stewart Hildebrand Cc: xen-devel@lists.xenproject.org, Andrew Cooper , George Dunlap , Jan Beulich , Julien Grall , Stefano Stabellini , Wei Liu Subject: Re: [PATCH v7 1/2] xen/vpci: header: status register handler Message-ID: References: <20230913143550.14565-1-stewart.hildebrand@amd.com> <20230913143550.14565-2-stewart.hildebrand@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Fri, Nov 17, 2023 at 01:40:37PM +0100, Roger Pau Monné wrote: > On Wed, Sep 13, 2023 at 10:35:46AM -0400, Stewart Hildebrand wrote: > > { > > - uint32_t val; > > - > > val = r->read(pdev, r->offset, r->private); > > + val &= ~r->rw1c_mask; > > data = merge_result(val, data, size, offset); > > } > > > > + data &= ~(r->rsvdz_mask | r->ro_mask); > > + data |= val & r->ro_mask; > > You cannot apply the register masks directly into the final value, you > need to offset and mask them as necessary, likewise for val, see > what's done in merge_result(). Never mind, I was wrong, there's no need to offset anything here. Roger.