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From: Andi Shyti <andi.shyti@linux.intel.com>
To: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [Intel-xe] [PATCH v3 1/3] drm/xe: Enable Fixed CCS mode setting
Date: Tue, 5 Dec 2023 22:57:13 +0100	[thread overview]
Message-ID: <ZW-cuW43D-RmXaci@ashyti-mobl2.lan> (raw)
In-Reply-To: <20231204053709.30013-2-niranjana.vishwanathapura@intel.com>

Hi Niranjana,

> +static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines)
> +{
> +	u32 mode = CCS_MODE_CSLICE_0_3_MASK; /* disable all by default */
> +	int num_slices = hweight32(CCS_MASK(gt));
> +	struct xe_device *xe = gt_to_xe(gt);
> +	int width, cslice = 0;
> +	u32 config = 0;
> +
> +	xe_assert(xe, xe_gt_ccs_mode_enabled(gt));
> +
> +	xe_assert(xe, num_engines && num_engines <= num_slices);
> +	xe_assert(xe, !(num_slices % num_engines));
> +
> +	/*
> +	 * Loop over all available slices and assign each a user engine.
> +	 * For example, if there are four compute slices available, the
> +	 * assignment of compute slices to compute engines would be,
> +	 *
> +	 * With 1 engine (ccs0):
> +	 *   slice 0, 1, 2, 3: ccs0
> +	 *
> +	 * With 2 engines (ccs0, ccs1):
> +	 *   slice 0, 2: ccs0
> +	 *   slice 1, 3: ccs1
> +	 *
> +	 * With 4 engines (ccs0, ccs1, ccs2, ccs3):
> +	 *   slice 0: ccs0
> +	 *   slice 1: ccs1
> +	 *   slice 2: ccs2
> +	 *   slice 3: ccs3
> +	 */
> +	for (width = num_slices / num_engines; width; width--) {
> +		struct xe_hw_engine *hwe;
> +		enum xe_hw_engine_id id;
> +
> +		for_each_hw_engine(hwe, gt, id) {
> +			if (hwe->class != XE_ENGINE_CLASS_COMPUTE)
> +				continue;
> +
> +			if (hwe->logical_instance >= num_engines)
> +				break;
> +
> +			config |= BIT(hwe->instance) << XE_HW_ENGINE_CCS0;
> +
> +			/* If a slice is fused off, leave disabled */
> +			while ((CCS_MASK(gt) & BIT(cslice)) == 0)
> +				cslice++;
> +
> +			mode &= ~CCS_MODE_CSLICE(cslice, CCS_MODE_CSLICE_MASK);
> +			mode |= CCS_MODE_CSLICE(cslice, hwe->instance);
> +			cslice++;
> +		}
> +	}

yeah... this looks correct!

> +
> +	xe_mmio_write32(gt, CCS_MODE, mode);
> +
> +	xe_gt_info(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n",
> +		   mode, config, num_engines, num_slices);
> +}
> +
> +void xe_gt_apply_ccs_mode(struct xe_gt *gt)
> +{
> +	if (!gt->ccs_mode)
> +		return;
> +
> +	__xe_gt_apply_ccs_mode(gt, gt->ccs_mode);
> +}

I thought you were going to remove this wrapper, but it's OK, I
don't really mind.

Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>

Thanks,
Andi

  reply	other threads:[~2023-12-05 21:57 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-04  5:37 [Intel-xe] [PATCH v3 0/3] drm/xe: Enable fixed CCS mode Niranjana Vishwanathapura
2023-12-04  5:37 ` [Intel-xe] [PATCH v3 1/3] drm/xe: Enable Fixed CCS mode setting Niranjana Vishwanathapura
2023-12-05 21:57   ` Andi Shyti [this message]
2023-12-07 21:45   ` Lucas De Marchi
2023-12-08 20:45     ` Niranjana Vishwanathapura
2023-12-04  5:37 ` [Intel-xe] [PATCH v3 2/3] drm/xe: Allow userspace to configure CCS mode Niranjana Vishwanathapura
2023-12-05 22:00   ` Andi Shyti
2023-12-04  5:37 ` [Intel-xe] [PATCH v3 3/3] drm/xe: Avoid any races around ccs_mode update Niranjana Vishwanathapura
2023-12-05 22:01   ` Andi Shyti
2023-12-04  6:53 ` [Intel-xe] ✓ CI.Patch_applied: success for drm/xe: Enable fixed CCS mode (rev2) Patchwork
2023-12-04  6:53 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-12-04  6:54 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-12-04  7:01 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-12-04  7:02 ` [Intel-xe] ✓ CI.Hooks: " Patchwork
2023-12-04  7:03 ` [Intel-xe] ✓ CI.checksparse: " Patchwork
2023-12-04  7:39 ` [Intel-xe] ✓ CI.BAT: " Patchwork

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