From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select
Date: Tue, 5 Dec 2023 17:01:55 +0200 [thread overview]
Message-ID: <ZW87Yys0Ji6NNG7e@intel.com> (raw)
In-Reply-To: <874jgw3j9q.fsf@intel.com>
On Tue, Dec 05, 2023 at 02:50:57PM +0200, Jani Nikula wrote:
> On Tue, 05 Dec 2023, "Shankar, Uma" <uma.shankar@intel.com> wrote:
> >> Yeah, writing 0 is done with an intention to disable it but that’s not the way to
> >> have this option disabled. Infact there is no reason to write to it for DP1.4+ if sink
> >> is compliant.
> >
> > The change looks ok and aligns with spec, its
> > Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>
> Ville, any further objections or concerns? Okay to merge?
I guess a small comment on why we're avoiding the BW_SET in there might
be good idea, lest we forget and try to reunify the two branches by
accident. But otherwise seems fine.
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2023-12-05 15:02 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-01 13:41 [Intel-gfx] [PATCH] drm/i915/edp: don't write to DP_LINK_BW_SET when using rate select Jani Nikula
2023-12-01 14:41 ` Ville Syrjälä
2023-12-04 9:57 ` Jani Nikula
2023-12-04 13:59 ` Manna, Animesh
2023-12-04 16:34 ` Shankar, Uma
2023-12-04 16:48 ` Jani Nikula
2023-12-04 16:52 ` Shankar, Uma
2023-12-05 12:00 ` Shankar, Uma
2023-12-05 12:50 ` Jani Nikula
2023-12-05 15:01 ` Ville Syrjälä [this message]
2023-12-01 23:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2023-12-03 4:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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