From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
Andrew Cooper <andrew.cooper3@citrix.com>, Wei Liu <wl@xen.org>
Subject: Re: [PATCH v3 5/6] x86/vPIC: vpic_elcr_mask() master bit 2 control
Date: Tue, 5 Dec 2023 18:29:24 +0100 [thread overview]
Message-ID: <ZW9d9MK6l6GwXo60@macbook> (raw)
In-Reply-To: <09fc4c14-07e8-4e59-a23e-bb295125f25a@suse.com>
On Tue, Nov 28, 2023 at 11:35:46AM +0100, Jan Beulich wrote:
> Master bit 2 is treated specially: We force it set, but we don't expose
> the bit being set to the guest. While right now the read and write
> handling can easily use the fixed mask, the restore input checking that
> is about to be put in place wants to use the inverted mask to prove that
> no bits are unduly set. That will require master bit 2 to be set. Otoh
> the read path requires the bit to be clear (the bit can have either
> value for the use on the write path). Hence allow use sites control over
> that bit.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> ---
> v3: New, split from larger patch.
> ---
> I'm certainly open to naming suggestions for the new macro parameter.
> "mb2" can certainly be misleading as to Multiboot 2. Yet "master_bit_2"
> it too long for my taste, not the least because of the macro then
> needing to be split across lines.
Let's leave it as mb2, I think given the context it is difficult to
mislead this code as having anything to do with multiboot.
>
> --- a/xen/arch/x86/hvm/vpic.c
> +++ b/xen/arch/x86/hvm/vpic.c
> @@ -41,7 +41,7 @@
> #define vpic_lock(v) spin_lock(__vpic_lock(v))
> #define vpic_unlock(v) spin_unlock(__vpic_lock(v))
> #define vpic_is_locked(v) spin_is_locked(__vpic_lock(v))
> -#define vpic_elcr_mask(v) ((v)->is_master ? 0xf8 : 0xde)
> +#define vpic_elcr_mask(v, mb2) ((v)->is_master ? 0xf8 | ((mb2) << 2) : 0xde)
>
> /* Return the highest priority found in mask. Return 8 if none. */
> #define VPIC_PRIO_NONE 8
> @@ -387,7 +387,7 @@ static int cf_check vpic_intercept_elcr_
> if ( dir == IOREQ_WRITE )
> {
> /* Some IRs are always edge trig. Slave IR is always level trig. */
> - data = (*val >> shift) & vpic_elcr_mask(vpic);
> + data = (*val >> shift) & vpic_elcr_mask(vpic, 1);
Not that it matters much, but I think you could use
vpic_elcr_mask(vpic, 0) to strictly keep the same behavior as
before?
> if ( vpic->is_master )
> data |= 1 << 2;
Since the bit is forcefully set here anyway.
Regardless:
Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
Thanks, Roger.
next prev parent reply other threads:[~2023-12-05 17:29 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-28 10:32 [PATCH v3 0/6] x86/HVM: load state checking Jan Beulich
2023-11-28 10:33 ` [PATCH v3 1/6] x86/HVM: introduce hvm_get_entry() Jan Beulich
2023-11-28 10:34 ` [PATCH v3 2/6] x86/HVM: split restore state checking from state loading Jan Beulich
2023-12-04 17:27 ` Roger Pau Monné
2023-12-05 8:52 ` Jan Beulich
2023-12-05 14:29 ` Roger Pau Monné
2023-12-05 14:59 ` Jan Beulich
2023-12-05 15:55 ` Roger Pau Monné
2023-12-06 7:27 ` Jan Beulich
2023-12-11 10:46 ` Roger Pau Monné
2023-12-11 11:31 ` Jan Beulich
2023-12-11 12:43 ` Roger Pau Monné
2023-12-11 13:15 ` Jan Beulich
2023-11-28 10:34 ` [PATCH v3 3/6] x86/HVM: adjust save/restore hook registration for optional check handler Jan Beulich
2023-11-28 10:35 ` [PATCH v3 4/6] x86/vPIT: check values loaded from state save record Jan Beulich
2023-12-04 17:46 ` Roger Pau Monné
2023-11-28 10:35 ` [PATCH v3 5/6] x86/vPIC: vpic_elcr_mask() master bit 2 control Jan Beulich
2023-12-05 17:29 ` Roger Pau Monné [this message]
2023-12-06 7:22 ` Jan Beulich
2023-11-28 10:36 ` [PATCH v3 6/6] x86/vPIC: check values loaded from state save record Jan Beulich
2023-12-05 17:41 ` Roger Pau Monné
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