From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8643C8C4; Mon, 27 Nov 2023 12:42:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=none Received: by smtp.kernel.org (Postfix) with ESMTPSA id 07870C433C9; Mon, 27 Nov 2023 12:42:43 +0000 (UTC) Date: Mon, 27 Nov 2023 12:42:41 +0000 From: Catalin Marinas To: Jason Gunthorpe Cc: Mark Rutland , Leon Romanovsky , Arnd Bergmann , linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rdma@vger.kernel.org, llvm@lists.linux.dev, Michael Guralnik , Nathan Chancellor , Nick Desaulniers , Will Deacon Subject: Re: [PATCH rdma-next 1/2] arm64/io: add memcpy_toio_64 Message-ID: References: <20231124122352.GB436702@nvidia.com> Precedence: bulk X-Mailing-List: linux-arch@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231124122352.GB436702@nvidia.com> On Fri, Nov 24, 2023 at 08:23:52AM -0400, Jason Gunthorpe wrote: > On Fri, Nov 24, 2023 at 10:16:15AM +0000, Mark Rutland wrote: > > On Thu, Nov 23, 2023 at 09:04:31PM +0200, Leon Romanovsky wrote: > > > From: Jason Gunthorpe [...] > > > Provide a new generic function memcpy_toio_64() which should reliably > > > generate the needed instructions for the architecture, assuming address > > > alignment. As the usual need for this operation is performance sensitive a > > > fast inline implementation is preferred. > > > > There is *no* architectural sequence that is guaranteed to reliably generate a > > 64-byte TLP, and this sequence won't guarnatee that (e.g. even if the CPU > > *always* merged adjacent stores, we can take an interrupt mid-sequence that > > would prevent that). > > WC is not guaranteed on any arch, that is well known. > > The HW has means to handle fragmented TLPs, it just hurts performance > when it happens. "reliable" here means we'd like to see something like > a > 90% chance of the large TLP instead of the < 1% chance with the C > loop. > > Future ARM CPUs have the ST64B instruction which does provide the > architectural guarantee, and x86 has a similar guaranteed instruction > now too. > > > What's the actual requirement here? Is this just for performance? > > Yes, just performance. Do you have any rough numbers (percentage)? It's highly microarchitecture-dependent until we get the ST64B instruction. More of a bike-shedding, I wonder whether the __iowrite*_copy() semantics are better suited for what you need in terms of ordering (not that mempcy_toio() to Normal NC memory gives us any ordering). -- Catalin From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C2A72C4167B for ; Mon, 27 Nov 2023 12:43:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XjUj60Jg63MVDaPV33WMa44cO7uEBLfsHFSS3ug3Tng=; b=DdNLYJN2p3yGv1 7L+7N9IU+yMotLubDjH7xBrADSVKnHiSfAPkkm3AMRtOAa/PErFhxTliYpgXUWWthQy7JhdvYc+mm 7z9zQSpCb4j1cmRKJqMC5vZANmIWrDaKX1LcaMBUlQNoVWx9m/O6dA8lxX7dmPqbGZMDRfmuQGiqV 8pHgZ5kz6SyuKi0jwEzrPBL5jpxZDjIsRtDNP6/7gEFwjQ264jPDyuS584JedIjoPrzV60F6gp059 5uMAdvobgjHMREC1i/s8jREcH5d04p+fdsard/+rXa35OOkrtHD6ZfIo8yk6FuNRvn/vaV6gXh6nn KmOCkTZCxct96irZKXhw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r7awt-002TY4-2c; Mon, 27 Nov 2023 12:42:51 +0000 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r7awr-002TXS-07 for linux-arm-kernel@lists.infradead.org; Mon, 27 Nov 2023 12:42:50 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by ams.source.kernel.org (Postfix) with ESMTP id F414BB80B53; Mon, 27 Nov 2023 12:42:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 07870C433C9; Mon, 27 Nov 2023 12:42:43 +0000 (UTC) Date: Mon, 27 Nov 2023 12:42:41 +0000 From: Catalin Marinas To: Jason Gunthorpe Cc: Mark Rutland , Leon Romanovsky , Arnd Bergmann , linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rdma@vger.kernel.org, llvm@lists.linux.dev, Michael Guralnik , Nathan Chancellor , Nick Desaulniers , Will Deacon Subject: Re: [PATCH rdma-next 1/2] arm64/io: add memcpy_toio_64 Message-ID: References: <20231124122352.GB436702@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20231124122352.GB436702@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231127_044249_231424_0F3E5AF4 X-CRM114-Status: GOOD ( 17.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Nov 24, 2023 at 08:23:52AM -0400, Jason Gunthorpe wrote: > On Fri, Nov 24, 2023 at 10:16:15AM +0000, Mark Rutland wrote: > > On Thu, Nov 23, 2023 at 09:04:31PM +0200, Leon Romanovsky wrote: > > > From: Jason Gunthorpe [...] > > > Provide a new generic function memcpy_toio_64() which should reliably > > > generate the needed instructions for the architecture, assuming address > > > alignment. As the usual need for this operation is performance sensitive a > > > fast inline implementation is preferred. > > > > There is *no* architectural sequence that is guaranteed to reliably generate a > > 64-byte TLP, and this sequence won't guarnatee that (e.g. even if the CPU > > *always* merged adjacent stores, we can take an interrupt mid-sequence that > > would prevent that). > > WC is not guaranteed on any arch, that is well known. > > The HW has means to handle fragmented TLPs, it just hurts performance > when it happens. "reliable" here means we'd like to see something like > a > 90% chance of the large TLP instead of the < 1% chance with the C > loop. > > Future ARM CPUs have the ST64B instruction which does provide the > architectural guarantee, and x86 has a similar guaranteed instruction > now too. > > > What's the actual requirement here? Is this just for performance? > > Yes, just performance. Do you have any rough numbers (percentage)? It's highly microarchitecture-dependent until we get the ST64B instruction. More of a bike-shedding, I wonder whether the __iowrite*_copy() semantics are better suited for what you need in terms of ordering (not that mempcy_toio() to Normal NC memory gives us any ordering). -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel