From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="JddLwKVf" Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3C921AD for ; Fri, 1 Dec 2023 15:59:07 -0800 (PST) Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1d0477a0062so56285ad.0 for ; Fri, 01 Dec 2023 15:59:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1701475147; x=1702079947; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=lGsmf0A9APK6VsKgIpT+PFWswpLSWAbxrH99oWb1ZUM=; b=JddLwKVfaSCi5feRvMw9xntMQ/hlFhLd+bSRUlwLB435iE8P38VWte1hIl2N0YDq0j KGS9eYwmBGDK47azL0lLjLNVsMC5Rp8t6jG3J+XFMjznWdsNiBCFbvW7Hpdp2yl/wzW8 02SQyVdJT+rFc51CuI6lyFshN1xoSZJWUd+AhXwa6NKUeXP9u08pGGSK4CAomnu1mwxv NEnhNT0Hb3rKZqK4rRWuEEcDqX74ezm5b+EBQ27QTx/en1mOu8LLMu2PkS/KgzUfQB1n 8oH4FWLxohNGlL+jLhNcOeHGfT/qC0VcRGa5qSn03huTICNF1v3qbDFyZ/OwMgAPKf/H W8SQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701475147; x=1702079947; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=lGsmf0A9APK6VsKgIpT+PFWswpLSWAbxrH99oWb1ZUM=; b=QQvkKXarF1Z23001AO7cOkw4Rd+R74u0MLee/k9msTcFcN9h/UR3U8UtX7rtrbV8og Z5/gdRv1dSe8L1Gj4DBtvYWVkHace2Gb6FbGx8wODYobJjLJT7nW6w9unAbTnIKBHW74 zCKzL3nsPn0oraVuzO9FHqUA5pdbnkxM+yBK4wVNcTzumF6rQQbxIu79OEZYLbQTb0r9 wGPsq1qjNyp6A9LMZc7dSyyaTOSYsDsgEHYCN5AyeXNHPZPhFeTBpGXEK9yI7pvcXCIz hGtRSjnvaRQQo8KKCXOSfavh+tPEYPXv8Nk1BAZ8oD8zsVHqwO9uGAK8ESo+9GrrCf5y Gv/w== X-Gm-Message-State: AOJu0YxRIBABo/onp85kel7uc4NAwsKmYRr/FqLwZPEJ7Vxw1Aiim4iS ZW6pdmulq4k7ffsPOp1SCXT4mg== X-Google-Smtp-Source: AGHT+IGPxpntAuYnfsZtOtic8wadmmCmlzXRjc5vfw1JxQElpfR+kT3R6rvQIh9vsG1M33dTqc9LCg== X-Received: by 2002:a17:903:3247:b0:1cf:d2c5:af12 with SMTP id ji7-20020a170903324700b001cfd2c5af12mr350869plb.12.1701475146789; Fri, 01 Dec 2023 15:59:06 -0800 (PST) Received: from google.com (148.98.83.34.bc.googleusercontent.com. [34.83.98.148]) by smtp.gmail.com with ESMTPSA id u17-20020a170902e81100b001bdb85291casm3864016plg.208.2023.12.01.15.59.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Dec 2023 15:59:06 -0800 (PST) Date: Fri, 1 Dec 2023 15:59:02 -0800 From: William McVicker To: Peter Griffin Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, gregkh@linuxfoundation.org, jirislaby@kernel.org, cw00.choi@samsung.com, alim.akhtar@samsung.com, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org Subject: Re: [PATCH v5 15/20] watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bit Message-ID: References: <20231201160925.3136868-1-peter.griffin@linaro.org> <20231201160925.3136868-16-peter.griffin@linaro.org> Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231201160925.3136868-16-peter.griffin@linaro.org> On 12/01/2023, Peter Griffin wrote: > The WDT uses the CPU core signal DBGACK to determine whether the SoC > is running in debug mode or not. If the DBGACK signal is asserted and > DBGACK_MASK bit is enabled, then WDT output and interrupt is masked > (disabled). > > Presence of the DBGACK_MASK bit is determined by adding a new > QUIRK_HAS_DBGACK_BIT quirk. > > Signed-off-by: Peter Griffin Tested-by: Will McVicker --- I verified boot to a busybox console and that the watchdog probes. Regards, Will > --- > drivers/watchdog/s3c2410_wdt.c | 27 ++++++++++++++++++++++++--- > 1 file changed, 24 insertions(+), 3 deletions(-) > > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c > index 0b4bd883ff28..39f3489e41d6 100644 > --- a/drivers/watchdog/s3c2410_wdt.c > +++ b/drivers/watchdog/s3c2410_wdt.c > @@ -34,9 +34,10 @@ > > #define S3C2410_WTCNT_MAXCNT 0xffff > > -#define S3C2410_WTCON_RSTEN (1 << 0) > -#define S3C2410_WTCON_INTEN (1 << 2) > -#define S3C2410_WTCON_ENABLE (1 << 5) > +#define S3C2410_WTCON_RSTEN (1 << 0) > +#define S3C2410_WTCON_INTEN (1 << 2) > +#define S3C2410_WTCON_ENABLE (1 << 5) > +#define S3C2410_WTCON_DBGACK_MASK (1 << 16) > > #define S3C2410_WTCON_DIV16 (0 << 3) > #define S3C2410_WTCON_DIV32 (1 << 3) > @@ -100,12 +101,17 @@ > * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT) > * with "watchdog counter enable" bit. That bit should be set to make watchdog > * counter running. > + * > + * %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Setting the > + * DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode. > + * Debug mode is determined by the DBGACK CPU signal. > */ > #define QUIRK_HAS_WTCLRINT_REG (1 << 0) > #define QUIRK_HAS_PMU_MASK_RESET (1 << 1) > #define QUIRK_HAS_PMU_RST_STAT (1 << 2) > #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) > #define QUIRK_HAS_PMU_CNT_EN (1 << 4) > +#define QUIRK_HAS_DBGACK_BIT (1 << 5) > > /* These quirks require that we have a PMU register map */ > #define QUIRKS_HAVE_PMUREG \ > @@ -375,6 +381,19 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) > return 0; > } > > +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt) > +{ > + unsigned long wtcon; > + > + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)) > + return; > + > + /* disable watchdog outputs if CPU is in debug mode */ > + wtcon = readl(wdt->reg_base + S3C2410_WTCON); > + wtcon |= S3C2410_WTCON_DBGACK_MASK; > + writel(wtcon, wdt->reg_base + S3C2410_WTCON); > +} > + > static int s3c2410wdt_keepalive(struct watchdog_device *wdd) > { > struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); > @@ -700,6 +719,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev) > wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); > wdt->wdt_device.parent = dev; > > + s3c2410wdt_mask_dbgack(wdt); > + > /* > * If "tmr_atboot" param is non-zero, start the watchdog right now. Also > * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog. > -- > 2.43.0.rc2.451.g8631bc7472-goog > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A1947C4167B for ; Fri, 1 Dec 2023 23:59:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Dw7J3dqYg3flcWvc8eNOfz7x9MVcVSouT3g596QZG+E=; b=iHtpFs4TO2tNuh S40FCE9ZSYU6yd9XuA3PhcCPjQuscQGMK130QKRnqJ/ccNc/eEx7QRAqQiXBU4ralz7Yv+yn/8SgQ PcqKwDEhzAKSAPLYHoQVcPFHnrG1cG31Sa7xOJ9OYmj3plqLe0siauqcrBxBdaq5SFd0fgMxmv8Pq aAvzUtCMz1NEavDBjZ6hAAOz9JEHpxCnq23Vi/HO+f5YfshI6jrjWzZTda/Sqg6lGqwbZz+CpIRLo CGuVXysK8jUNjQdSsxfgAX4k6+Ci8CWGYZwe8wA4T3xxnXXojxPzcZMk/q4ym1gzQnnr40wzYuRKY bdeSS0lukDsx2iCBZcog==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1r9DPb-00EsXW-1m; Fri, 01 Dec 2023 23:59:11 +0000 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1r9DPY-00EsX4-2P for linux-arm-kernel@lists.infradead.org; Fri, 01 Dec 2023 23:59:10 +0000 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1d0477a0062so56265ad.0 for ; Fri, 01 Dec 2023 15:59:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1701475147; x=1702079947; darn=lists.infradead.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=lGsmf0A9APK6VsKgIpT+PFWswpLSWAbxrH99oWb1ZUM=; b=rqzfNXjCd2Zq07fE9BLN73NdBufi/jyB2wpDC4jqvW8+KOAEdWygwiwR+SkpFh9NRm iPN8fyVvw4yl6agtHoWBCHjrdjG+pTure2eYlHfslorbQW7XY+6rQqqwQJYzVgxKbvaa n8eJZlRFnOD21jqTZ6b1xTBAF4WaSc3fRDKXrOMH3Xn/Gs1gFcK1d5hi8ukqIj8suR5h Hhqx5hBbFXhBQmroG6JJPQrezj7WVesraCK4uxEhFOhcDk6/5ibGKVc4Rq7PFSd7Pczx 28eYTTwgftPUZ/2NEOlOM1ttcwRWfeA/nt8RQ3lexPSLQ+cpynCiQzxQPioTvDyBJPnF rdJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701475147; x=1702079947; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=lGsmf0A9APK6VsKgIpT+PFWswpLSWAbxrH99oWb1ZUM=; b=JYk2FD8aaNn6MszhbXwwkovHPJ2T7j0ywmCRwa0CzTjhrDqZ89SuCyDJ6uTxVowhZs qu6tUjVGItcl3lE6XBS2zaLTUhQt+d+qMOLEUi3HwiWT4SbkWyJTDimhT+ztZqfKFTWj yEYajDOv+F2kpDwsoAnfgmTTf7t44wcYEEYQdXn0Yyzu3Pj2mIEbkjgJLxNO+Ez0j/uY SxhnTgkFluyiTpCFlCpW+3TE+YbPTLsgLhU7gMEonBcDjY+tfP4HlpXRrg559QLQbDja FoUsdKyX2aE0utoOGbUy2G4yjFxLpAuHtfo1VWL2/nXaJvrYkfKh+pb31uK4ROXH7Uzu lcQg== X-Gm-Message-State: AOJu0Yww0fLDJK9INQ8PUpaJZK1MRuz1sJr9ZvvoYQkZIm4b5Iil1zXX dyqEwHYtnxfJqswMPH2Be+eSfw== X-Google-Smtp-Source: AGHT+IGPxpntAuYnfsZtOtic8wadmmCmlzXRjc5vfw1JxQElpfR+kT3R6rvQIh9vsG1M33dTqc9LCg== X-Received: by 2002:a17:903:3247:b0:1cf:d2c5:af12 with SMTP id ji7-20020a170903324700b001cfd2c5af12mr350869plb.12.1701475146789; Fri, 01 Dec 2023 15:59:06 -0800 (PST) Received: from google.com (148.98.83.34.bc.googleusercontent.com. [34.83.98.148]) by smtp.gmail.com with ESMTPSA id u17-20020a170902e81100b001bdb85291casm3864016plg.208.2023.12.01.15.59.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Dec 2023 15:59:06 -0800 (PST) Date: Fri, 1 Dec 2023 15:59:02 -0800 From: William McVicker To: Peter Griffin Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, gregkh@linuxfoundation.org, jirislaby@kernel.org, cw00.choi@samsung.com, alim.akhtar@samsung.com, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org Subject: Re: [PATCH v5 15/20] watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bit Message-ID: References: <20231201160925.3136868-1-peter.griffin@linaro.org> <20231201160925.3136868-16-peter.griffin@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20231201160925.3136868-16-peter.griffin@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20231201_155908_802051_8E47066C X-CRM114-Status: GOOD ( 26.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/01/2023, Peter Griffin wrote: > The WDT uses the CPU core signal DBGACK to determine whether the SoC > is running in debug mode or not. If the DBGACK signal is asserted and > DBGACK_MASK bit is enabled, then WDT output and interrupt is masked > (disabled). > > Presence of the DBGACK_MASK bit is determined by adding a new > QUIRK_HAS_DBGACK_BIT quirk. > > Signed-off-by: Peter Griffin Tested-by: Will McVicker --- I verified boot to a busybox console and that the watchdog probes. Regards, Will > --- > drivers/watchdog/s3c2410_wdt.c | 27 ++++++++++++++++++++++++--- > 1 file changed, 24 insertions(+), 3 deletions(-) > > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c > index 0b4bd883ff28..39f3489e41d6 100644 > --- a/drivers/watchdog/s3c2410_wdt.c > +++ b/drivers/watchdog/s3c2410_wdt.c > @@ -34,9 +34,10 @@ > > #define S3C2410_WTCNT_MAXCNT 0xffff > > -#define S3C2410_WTCON_RSTEN (1 << 0) > -#define S3C2410_WTCON_INTEN (1 << 2) > -#define S3C2410_WTCON_ENABLE (1 << 5) > +#define S3C2410_WTCON_RSTEN (1 << 0) > +#define S3C2410_WTCON_INTEN (1 << 2) > +#define S3C2410_WTCON_ENABLE (1 << 5) > +#define S3C2410_WTCON_DBGACK_MASK (1 << 16) > > #define S3C2410_WTCON_DIV16 (0 << 3) > #define S3C2410_WTCON_DIV32 (1 << 3) > @@ -100,12 +101,17 @@ > * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT) > * with "watchdog counter enable" bit. That bit should be set to make watchdog > * counter running. > + * > + * %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Setting the > + * DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode. > + * Debug mode is determined by the DBGACK CPU signal. > */ > #define QUIRK_HAS_WTCLRINT_REG (1 << 0) > #define QUIRK_HAS_PMU_MASK_RESET (1 << 1) > #define QUIRK_HAS_PMU_RST_STAT (1 << 2) > #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3) > #define QUIRK_HAS_PMU_CNT_EN (1 << 4) > +#define QUIRK_HAS_DBGACK_BIT (1 << 5) > > /* These quirks require that we have a PMU register map */ > #define QUIRKS_HAVE_PMUREG \ > @@ -375,6 +381,19 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en) > return 0; > } > > +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt) > +{ > + unsigned long wtcon; > + > + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)) > + return; > + > + /* disable watchdog outputs if CPU is in debug mode */ > + wtcon = readl(wdt->reg_base + S3C2410_WTCON); > + wtcon |= S3C2410_WTCON_DBGACK_MASK; > + writel(wtcon, wdt->reg_base + S3C2410_WTCON); > +} > + > static int s3c2410wdt_keepalive(struct watchdog_device *wdd) > { > struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd); > @@ -700,6 +719,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev) > wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); > wdt->wdt_device.parent = dev; > > + s3c2410wdt_mask_dbgack(wdt); > + > /* > * If "tmr_atboot" param is non-zero, start the watchdog right now. Also > * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog. > -- > 2.43.0.rc2.451.g8631bc7472-goog > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel