From: Pavel Machek <pavel@denx.de>
To: nobuhiro1.iwamatsu@toshiba.co.jp
Cc: biju.das.jz@bp.renesas.com, cip-dev@lists.cip-project.org,
pavel@denx.de, prabhakar.mahadev-lad.rj@bp.renesas.com
Subject: Re: [PATCH 5.10.y-cip 00/12] Add display/dsi/gpt/poeg clk support
Date: Thu, 7 Dec 2023 19:03:08 +0100 [thread overview]
Message-ID: <ZXII3AdJ3b3JLKCF@duo.ucw.cz> (raw)
In-Reply-To: <TYVPR01MB11245FE499E04243865C3667E928BA@TYVPR01MB11245.jpnprd01.prod.outlook.com>
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Hi!
> > Biju Das (12):
> > clk: renesas: rzg2l: Add FOUTPOSTDIV clk support
> > clk: renesas: rzg2l: Add PLL5_4 clk mux support
> > clk: renesas: rzg2l: Add DSI divider clk support
> > clk: renesas: r9a07g044: Add M1 clock support
> > clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support
> > clk: renesas: r9a07g044: Add M3 Clock support
> > clk: renesas: r9a07g044: Add M4 Clock support
> > clk: renesas: r9a07g044: Add LCDC clock and reset entries
> > clk: renesas: r9a07g044: Add DSI clock and reset entries
> > clk: renesas: r9a07g044: Add GPT clock and reset entry
> > clk: renesas: r9a07g044: Add POEG clock and reset entries
> > clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write
> >
>
> I reviewed this series, LGTM.
>
> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Thank you. Applied and pushed out.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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prev parent reply other threads:[~2023-12-07 18:03 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-07 10:54 [PATCH 5.10.y-cip 00/12] Add display/dsi/gpt/poeg clk support Biju Das
2023-12-07 10:54 ` [PATCH 5.10.y-cip 01/12] clk: renesas: rzg2l: Add FOUTPOSTDIV " Biju Das
2023-12-07 10:54 ` [PATCH 5.10.y-cip 02/12] clk: renesas: rzg2l: Add PLL5_4 clk mux support Biju Das
2023-12-07 10:54 ` [PATCH 5.10.y-cip 03/12] clk: renesas: rzg2l: Add DSI divider clk support Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 04/12] clk: renesas: r9a07g044: Add M1 clock support Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 05/12] clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 06/12] clk: renesas: r9a07g044: Add M3 Clock support Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 07/12] clk: renesas: r9a07g044: Add M4 " Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 08/12] clk: renesas: r9a07g044: Add LCDC clock and reset entries Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 09/12] clk: renesas: r9a07g044: Add DSI " Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 10/12] clk: renesas: r9a07g044: Add GPT clock and reset entry Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 11/12] clk: renesas: r9a07g044: Add POEG clock and reset entries Biju Das
2023-12-07 10:55 ` [PATCH 5.10.y-cip 12/12] clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write Biju Das
2023-12-07 11:17 ` [PATCH 5.10.y-cip 00/12] Add display/dsi/gpt/poeg clk support Pavel Machek
2023-12-07 13:49 ` nobuhiro1.iwamatsu
2023-12-07 18:03 ` Pavel Machek [this message]
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