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From: Zhao Liu <zhao1.liu@intel.com>
To: Xin Li <xin3.li@intel.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
	richard.henderson@linaro.org, pbonzini@redhat.com,
	eduardo@habkost.net, seanjc@google.com, chao.gao@intel.com,
	hpa@zytor.com, xiaoyao.li@intel.com, weijiang.yang@intel.com
Subject: Re: [PATCH v3 2/6] target/i386: mark CR4.FRED not reserved
Date: Fri, 22 Dec 2023 17:26:40 +0800	[thread overview]
Message-ID: <ZYVWUHt6EAVN9YMp@intel.com> (raw)
In-Reply-To: <20231109072012.8078-3-xin3.li@intel.com>

On Wed, Nov 08, 2023 at 11:20:08PM -0800, Xin Li wrote:
> Date: Wed,  8 Nov 2023 23:20:08 -0800
> From: Xin Li <xin3.li@intel.com>
> Subject: [PATCH v3 2/6] target/i386: mark CR4.FRED not reserved
> X-Mailer: git-send-email 2.42.0
> 
> The CR4.FRED bit, i.e., CR4[32], is no longer a reserved bit when FRED
> is exposed to guests, otherwise it is still a reserved bit.
> 
> Tested-by: Shan Kang <shan.kang@intel.com>
> Signed-off-by: Xin Li <xin3.li@intel.com>
> ---

Reviewed-by: Zhao Liu <zhao1.liu@intel.com>

>  target/i386/cpu.h | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 5faf00551d..e210957cba 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -262,6 +262,12 @@ typedef enum X86Seg {
>  #define CR4_PKE_MASK   (1U << 22)
>  #define CR4_PKS_MASK   (1U << 24)
>  
> +#ifdef TARGET_X86_64
> +#define CR4_FRED_MASK   (1ULL << 32)
> +#else
> +#define CR4_FRED_MASK   0
> +#endif
> +
>  #define CR4_RESERVED_MASK \
>  (~(target_ulong)(CR4_VME_MASK | CR4_PVI_MASK | CR4_TSD_MASK \
>                  | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \
> @@ -269,7 +275,8 @@ typedef enum X86Seg {
>                  | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK | CR4_UMIP_MASK \
>                  | CR4_LA57_MASK \
>                  | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \
> -                | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK))
> +                | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK \
> +                | CR4_FRED_MASK))
>  
>  #define DR6_BD          (1 << 13)
>  #define DR6_BS          (1 << 14)
> @@ -2520,6 +2527,9 @@ static inline uint64_t cr4_reserved_bits(CPUX86State *env)
>      if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) {
>          reserved_bits |= CR4_PKS_MASK;
>      }
> +    if (!(env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED)) {
> +        reserved_bits |= CR4_FRED_MASK;
> +    }
>      return reserved_bits;
>  }
>  
> -- 
> 2.42.0
> 
> 

  reply	other threads:[~2023-12-22  9:13 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-09  7:20 [PATCH v3 0/6] target/i386: add support for FRED Xin Li
2023-11-09  7:20 ` [PATCH v3 1/6] target/i386: add support for FRED in CPUID enumeration Xin Li
2023-12-14  8:15   ` Wu, Dan1
2023-12-21  8:27     ` Li, Xin3
2023-12-22  3:03       ` [PATCH v3A " Xin Li
2023-12-22  7:34         ` Zhao Liu
2023-12-22  8:15           ` Zhao Liu
2023-12-22  8:24             ` Li, Xin3
2023-12-22  8:47               ` Liu, Zhao1
2023-11-09  7:20 ` [PATCH v3 2/6] target/i386: mark CR4.FRED not reserved Xin Li
2023-12-22  9:26   ` Zhao Liu [this message]
2023-11-09  7:20 ` [PATCH v3 3/6] target/i386: add the secondary VM exit controls MSR Xin Li
2023-11-09  7:20 ` [PATCH v3 4/6] target/i386: add support for VMX FRED controls Xin Li
2024-06-06  9:00   ` Paolo Bonzini
2024-06-07 14:13     ` Li, Xin3
2023-11-09  7:20 ` [PATCH v3 5/6] target/i386: enumerate VMX nested-exception support Xin Li
2023-11-09  7:20 ` [PATCH v3 6/6] target/i386: Add get/set/migrate support for FRED MSRs Xin Li

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