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From: Christoph Winklhofer <cj.winklhofer@gmail.com>
To: Rob Herring <robh@kernel.org>
Cc: krzysztof.kozlowski@linaro.org, conor+dt@kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 1/2] dt-bindings: w1: UART 1-wire bus
Date: Sat, 23 Dec 2023 10:44:53 +0100	[thread overview]
Message-ID: <ZYasFZhjsjJ7PC61@cjw-notebook> (raw)
In-Reply-To: <20231221205958.GA73493-robh@kernel.org>

On Thu, Dec 21, 2023 at 02:59:58PM -0600, Rob Herring wrote:
> On Thu, Dec 21, 2023 at 07:50:47AM +0100, Christoph Winklhofer wrote:
> > Add device tree binding for UART 1-wire bus.
> > 
> > Signed-off-by: Christoph Winklhofer <cj.winklhofer@gmail.com>
> > ---
> >  .../devicetree/bindings/w1/w1-uart.yaml       | 44 +++++++++++++++++++
> >  1 file changed, 44 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/w1/w1-uart.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/w1/w1-uart.yaml b/Documentation/devicetree/bindings/w1/w1-uart.yaml
> > new file mode 100644
> > index 000000000000..93d83c42c407
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/w1/w1-uart.yaml
> > @@ -0,0 +1,44 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/w1/w1-uart.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: UART 1-Wire Bus
> > +
> > +maintainers:
> > +  - Christoph Winklhofer <cj.winklhofer@gmail.com>
> > +
> > +description: |
> > +  UART 1-wire bus. Utilizes the UART interface via the Serial Device Bus
> > +  to create the 1-Wire timing patterns.
> > +
> > +  The UART peripheral must support full-duplex and operate in open-drain
> > +  mode. The timing patterns are generated by a specific combination of
> > +  baud-rate and transmitted byte, which corresponds to a 1-Wire read bit,
> > +  write bit or reset pulse.
> > +
> > +  The default baud-rate for reset and presence detection is 9600 and for
> > +  a 1-Wire read or write operation 115200. In case the actual baud-rate
> > +  is different from the requested one, the transmitted byte is adapted
> > +  to generate the 1-Wire timing patterns.
> > +
> > +  https://www.analog.com/en/technical-articles/using-a-uart-to-implement-a-1wire-bus-master.html
> > +
> > +
> > +properties:
> > +  compatible:
> > +    const: w1-uart
> > +
> > +required:
> > +  - compatible
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    serial {
> > +      onewire {
> 
> Have you tried this in an actual DT? Assuming the UART node has a 
> schema, it should be a warning because child node names are explicit in 
> serial.yaml unfortunately. IOW, you need to add "onewire" to 
> serial.yaml.
>

Thank you! It was tested on an older DT with the wildcard pattern. I
updated my test-system and now get the warning. On the Raspberry PI, 
a DT overlay was used, in this case there is no warning with:

  make CHECK_DTBS=y overlays/w1-uart.dtbo ARCH=arm

Is it possible to do a validation for a DT overlay? Since the overlay
may be incomplete, only existing nodes or properties could be checked.

Thanks!
Christoph

  reply	other threads:[~2023-12-23  9:44 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-21  6:50 [PATCH v1 0/2] w1: add UART w1 bus driver Christoph Winklhofer
2023-12-21  6:50 ` [PATCH v1 1/2] dt-bindings: w1: UART 1-wire bus Christoph Winklhofer
2023-12-21 20:59   ` Rob Herring
2023-12-23  9:44     ` Christoph Winklhofer [this message]
2023-12-21  6:50 ` [PATCH v1 2/2] w1: add UART w1 bus driver Christoph Winklhofer
2023-12-21 21:13 ` [PATCH v1 0/2] " Krzysztof Kozlowski
2023-12-23  9:54   ` Christoph Winklhofer

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