From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EA4F047A52; Mon, 8 Jan 2024 14:03:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 285F8C15; Mon, 8 Jan 2024 06:03:54 -0800 (PST) Received: from localhost (ionvoi01-desktop.cambridge.arm.com [10.2.78.69]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CC12E3F64C; Mon, 8 Jan 2024 06:03:07 -0800 (PST) Date: Mon, 8 Jan 2024 14:03:06 +0000 From: Ionela Voinescu To: "lihuisong (C)" Cc: Vanshidhar Konda , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, rafael@kernel.org, beata.michalska@arm.com, sumitg@nvidia.com, zengheng4@huawei.com, yang@os.amperecomputing.com, will@kernel.org, sudeep.holla@arm.com, liuyonglong@huawei.com, zhanjie9@hisilicon.com, "linux-acpi@vger.kernel.org" Subject: Re: [PATCH] cpufreq: CPPC: Resolve the large frequency discrepancy from cpuinfo_cur_freq Message-ID: References: <20231212072617.14756-1-lihuisong@huawei.com> <9428a1ed-ba4d-1fe6-63e8-11e152bf1f09@huawei.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Hi, On Friday 05 Jan 2024 at 15:04:47 (+0800), lihuisong (C) wrote: > Hi Vanshi, > > 在 2024/1/5 8:48, Vanshidhar Konda 写道: > > On Thu, Jan 04, 2024 at 05:36:51PM +0800, lihuisong (C) wrote: > > > > > > 在 2024/1/4 1:53, Ionela Voinescu 写道: > > > > Hi, > > > > > > > > On Tuesday 12 Dec 2023 at 15:26:17 (+0800), Huisong Li wrote: > > > > > Many developers found that the cpu current frequency is greater than > > > > > the maximum frequency of the platform, please see [1], [2] and [3]. > > > > > > > > > > In the scenarios with high memory access pressure, the patch [1] has > > > > > proved the significant latency of cpc_read() which is used to obtain > > > > > delivered and reference performance counter cause an absurd frequency. > > > > > The sampling interval for this counters is very critical and > > > > > is expected > > > > > to be equal. However, the different latency of cpc_read() has a direct > > > > > impact on their sampling interval. > > > > > > > > > Would this [1] alternative solution work for you? > > > It would work for me AFAICS. > > > Because the "arch_freq_scale" is also from AMU core and constant > > > counter, and read together. > > > But, from their discuss line, it seems that there are some tricky > > > points to clarify or consider. > > > > I think the changes in [1] would work better when CPUs may be idle. With > > this > > patch we would have to wake any core that is in idle state to read the > > AMU > > counters. Worst case, if core 0 is trying to read the CPU frequency of > > all > > cores, it may need to wake up all the other cores to read the AMU > > counters. > From the approach in [1], if all CPUs (one or more cores) under one policy > are idle, they still cannot be obtained the CPU frequency, right? > In this case, the [1] API will return 0 and have to back to call > cpufreq_driver->get() for cpuinfo_cur_freq. > Then we still need to face the issue this patch mentioned. With the implementation at [1], arch_freq_get_on_cpu() will not return 0 for idle CPUs and the get() callback will not be called to wake up the CPUs. Worst case, arch_freq_get_on_cpu() will return a frequency based on the AMU counter values obtained on the last tick on that CPU. But if that CPU is not a housekeeping CPU, a housekeeping CPU in the same policy will be selected, as it would have had a more recent tick, and therefore a more recent frequency value for the domain. I understand that the frequency returned here will not be up to date, but there's no proper frequency feedback for an idle CPU. If one only wakes up a CPU to sample counters, before the CPU goes back to sleep, the obtained frequency feedback is meaningless. > > For systems with 128 cores or more, this could be very expensive and > > happen > > very frequently. > > > > AFAICS, the approach in [1] would avoid this cost. > But the CPU frequency is just an average value for the last tick period > instead of the current one the CPU actually runs at. > In addition, there are some conditions to use 'arch_freq_scale' in this > approach. What are the conditions you are referring to? > So I'm not sure if this approach can entirely cover the frequency > discrepancy issue. Unfortunately there is no perfect frequency feedback. By the time you observe/use the value of scaling_cur_freq/cpuinfo_cur_freq, the frequency of the CPU might have already changed. Therefore, an average value might be a better indication of the recent performance level of a CPU. Would you be able to test [1] on your platform and usecase? Many thanks, Ionela. > > /Huisong > > > > > > > > > [1] https://lore.kernel.org/lkml/20231127160838.1403404-1-beata.michalska@arm.com/ > > > > > > > > Thanks, > > > > Ionela. > > > > > > > > > This patch adds a interface, cpc_read_arch_counters_on_cpu, to read > > > > > delivered and reference performance counter together. According to my > > > > > test[4], the discrepancy of cpu current frequency in the > > > > > scenarios with > > > > > high memory access pressure is lower than 0.2% by stress-ng > > > > > application. > > > > > > > > > > [1] https://lore.kernel.org/all/20231025093847.3740104-4-zengheng4@huawei.com/ > > > > > [2] https://lore.kernel.org/all/20230328193846.8757-1-yang@os.amperecomputing.com/ > > > > > [3] > > > > > https://lore.kernel.org/all/20230418113459.12860-7-sumitg@nvidia.com/ > > > > > > > > > > [4] My local test: > > > > > The testing platform enable SMT and include 128 logical CPU in total, > > > > > and CPU base frequency is 2.7GHz. Reading "cpuinfo_cur_freq" for each > > > > > physical core on platform during the high memory access pressure from > > > > > stress-ng, and the output is as follows: > > > > >   0: 2699133     2: 2699942     4: 2698189     6: 2704347 > > > > >   8: 2704009    10: 2696277    12: 2702016    14: 2701388 > > > > >  16: 2700358    18: 2696741    20: 2700091    22: 2700122 > > > > >  24: 2701713    26: 2702025    28: 2699816    30: 2700121 > > > > >  32: 2700000    34: 2699788    36: 2698884    38: 2699109 > > > > >  40: 2704494    42: 2698350    44: 2699997    46: 2701023 > > > > >  48: 2703448    50: 2699501    52: 2700000    54: 2699999 > > > > >  56: 2702645    58: 2696923    60: 2697718    62: 2700547 > > > > >  64: 2700313    66: 2700000    68: 2699904    70: 2699259 > > > > >  72: 2699511    74: 2700644    76: 2702201    78: 2700000 > > > > >  80: 2700776    82: 2700364    84: 2702674    86: 2700255 > > > > >  88: 2699886    90: 2700359    92: 2699662    94: 2696188 > > > > >  96: 2705454    98: 2699260   100: 2701097   102: 2699630 > > > > > 104: 2700463   106: 2698408   108: 2697766   110: 2701181 > > > > > 112: 2699166   114: 2701804   116: 2701907   118: 2701973 > > > > > 120: 2699584   122: 2700474   124: 2700768   126: 2701963 > > > > > > > > > > Signed-off-by: Huisong Li > > > > > --- > > > > >  arch/arm64/kernel/topology.c | 43 > > > > > ++++++++++++++++++++++++++++++++++-- > > > > >  drivers/acpi/cppc_acpi.c     | 22 +++++++++++++++--- > > > > >  include/acpi/cppc_acpi.h     |  5 +++++ > > > > >  3 files changed, 65 insertions(+), 5 deletions(-) > > > > > > > > > > diff --git a/arch/arm64/kernel/topology.c > > > > > b/arch/arm64/kernel/topology.c > > > > > index 7d37e458e2f5..c3122154d738 100644 > > > > > --- a/arch/arm64/kernel/topology.c > > > > > +++ b/arch/arm64/kernel/topology.c > > > > > @@ -299,6 +299,11 @@ core_initcall(init_amu_fie); > > > > >  #ifdef CONFIG_ACPI_CPPC_LIB > > > > >  #include > > > > > +struct amu_counters { > > > > > +    u64 corecnt; > > > > > +    u64 constcnt; > > > > > +}; > > > > > + > > > > >  static void cpu_read_corecnt(void *val) > > > > >  { > > > > >      /* > > > > > @@ -322,8 +327,27 @@ static void cpu_read_constcnt(void *val) > > > > >                0UL : read_constcnt(); > > > > >  } > > > > > +static void cpu_read_amu_counters(void *data) > > > > > +{ > > > > > +    struct amu_counters *cnt = (struct amu_counters *)data; > > > > > + > > > > > +    /* > > > > > +     * The running time of the this_cpu_has_cap() might > > > > > have a couple of > > > > > +     * microseconds and is significantly increased to tens > > > > > of microseconds. > > > > > +     * But AMU core and constant counter need to be read > > > > > togeter without any > > > > > +     * time interval to reduce the calculation discrepancy > > > > > using this counters. > > > > > +     */ > > > > > +    if (this_cpu_has_cap(ARM64_WORKAROUND_2457168)) { > > > > > +        cnt->corecnt = read_corecnt(); > > > > > +        cnt->constcnt = 0; > > > > > +    } else { > > > > > +        cnt->corecnt = read_corecnt(); > > > > > +        cnt->constcnt = read_constcnt(); > > > > > +    } > > > > > +} > > > > > + > > > > >  static inline > > > > > -int counters_read_on_cpu(int cpu, smp_call_func_t func, u64 *val) > > > > > +int counters_read_on_cpu(int cpu, smp_call_func_t func, void *data) > > > > >  { > > > > >      /* > > > > >       * Abort call on counterless CPU or when interrupts are > > > > > @@ -335,7 +359,7 @@ int counters_read_on_cpu(int cpu, > > > > > smp_call_func_t func, u64 *val) > > > > >      if (WARN_ON_ONCE(irqs_disabled())) > > > > >          return -EPERM; > > > > > -    smp_call_function_single(cpu, func, val, 1); > > > > > +    smp_call_function_single(cpu, func, data, 1); > > > > >      return 0; > > > > >  } > > > > > @@ -364,6 +388,21 @@ bool cpc_ffh_supported(void) > > > > >      return true; > > > > >  } > > > > > +int cpc_read_arch_counters_on_cpu(int cpu, u64 *delivered, > > > > > u64 *reference) > > > > > +{ > > > > > +    struct amu_counters cnts = {0}; > > > > > +    int ret; > > > > > + > > > > > +    ret = counters_read_on_cpu(cpu, cpu_read_amu_counters, &cnts); > > > > > +    if (ret) > > > > > +        return ret; > > > > > + > > > > > +    *delivered = cnts.corecnt; > > > > > +    *reference = cnts.constcnt; > > > > > + > > > > > +    return 0; > > > > > +} > > > > > + > > > > >  int cpc_read_ffh(int cpu, struct cpc_reg *reg, u64 *val) > > > > >  { > > > > >      int ret = -EOPNOTSUPP; > > > > > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c > > > > > index 7ff269a78c20..f303fabd7cfe 100644 > > > > > --- a/drivers/acpi/cppc_acpi.c > > > > > +++ b/drivers/acpi/cppc_acpi.c > > > > > @@ -1299,6 +1299,11 @@ bool cppc_perf_ctrs_in_pcc(void) > > > > >  } > > > > >  EXPORT_SYMBOL_GPL(cppc_perf_ctrs_in_pcc); > > > > > +int __weak cpc_read_arch_counters_on_cpu(int cpu, u64 > > > > > *delivered, u64 *reference) > > > > > +{ > > > > > +    return 0; > > > > > +} > > > > > + > > > > >  /** > > > > >   * cppc_get_perf_ctrs - Read a CPU's performance feedback counters. > > > > >   * @cpunum: CPU from which to read counters. > > > > > @@ -1313,7 +1318,8 @@ int cppc_get_perf_ctrs(int cpunum, > > > > > struct cppc_perf_fb_ctrs *perf_fb_ctrs) > > > > >          *ref_perf_reg, *ctr_wrap_reg; > > > > >      int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); > > > > >      struct cppc_pcc_data *pcc_ss_data = NULL; > > > > > -    u64 delivered, reference, ref_perf, ctr_wrap_time; > > > > > +    u64 delivered = 0, reference = 0; > > > > > +    u64 ref_perf, ctr_wrap_time; > > > > >      int ret = 0, regs_in_pcc = 0; > > > > >      if (!cpc_desc) { > > > > > @@ -1350,8 +1356,18 @@ int cppc_get_perf_ctrs(int cpunum, > > > > > struct cppc_perf_fb_ctrs *perf_fb_ctrs) > > > > >          } > > > > >      } > > > > > -    cpc_read(cpunum, delivered_reg, &delivered); > > > > > -    cpc_read(cpunum, reference_reg, &reference); > > > > > +    if (cpc_ffh_supported()) { > > > > > +        ret = cpc_read_arch_counters_on_cpu(cpunum, > > > > > &delivered, &reference); > > > > > +        if (ret) { > > > > > +            pr_debug("read arch counters failed, ret=%d.\n", ret); > > > > > +            ret = 0; > > > > > +        } > > > > > +    } > > > > > +    if (!delivered || !reference) { > > > > > +        cpc_read(cpunum, delivered_reg, &delivered); > > > > > +        cpc_read(cpunum, reference_reg, &reference); > > > > > +    } > > > > > + > > > > >      cpc_read(cpunum, ref_perf_reg, &ref_perf); > > > > >      /* > > > > > diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h > > > > > index 6126c977ece0..07d4fd82d499 100644 > > > > > --- a/include/acpi/cppc_acpi.h > > > > > +++ b/include/acpi/cppc_acpi.h > > > > > @@ -152,6 +152,7 @@ extern bool cpc_ffh_supported(void); > > > > >  extern bool cpc_supported_by_cpu(void); > > > > >  extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val); > > > > >  extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val); > > > > > +extern int cpc_read_arch_counters_on_cpu(int cpu, u64 > > > > > *delivered, u64 *reference); > > > > >  extern int cppc_get_epp_perf(int cpunum, u64 *epp_perf); > > > > >  extern int cppc_set_epp_perf(int cpu, struct > > > > > cppc_perf_ctrls *perf_ctrls, bool enable); > > > > >  extern int cppc_get_auto_sel_caps(int cpunum, struct > > > > > cppc_perf_caps *perf_caps); > > > > > @@ -209,6 +210,10 @@ static inline int cpc_write_ffh(int > > > > > cpunum, struct cpc_reg *reg, u64 val) > > > > >  { > > > > >      return -ENOTSUPP; > > > > >  } > > > > > +static inline int cpc_read_arch_counters_on_cpu(int cpu, > > > > > u64 *delivered, u64 *reference) > > > > > +{ > > > > > +    return -EOPNOTSUPP; > > > > > +} > > > > >  static inline int cppc_set_epp_perf(int cpu, struct > > > > > cppc_perf_ctrls *perf_ctrls, bool enable) > > > > >  { > > > > >      return -ENOTSUPP; > > > > > -- > > > > > 2.33.0 > > > > > > > > > . > > > > > > _______________________________________________ > > > linux-arm-kernel mailing list > > > linux-arm-kernel@lists.infradead.org > > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > > > > . 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usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CC12E3F64C; Mon, 8 Jan 2024 06:03:07 -0800 (PST) Date: Mon, 8 Jan 2024 14:03:06 +0000 From: Ionela Voinescu To: "lihuisong (C)" Cc: Vanshidhar Konda , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, rafael@kernel.org, beata.michalska@arm.com, sumitg@nvidia.com, zengheng4@huawei.com, yang@os.amperecomputing.com, will@kernel.org, sudeep.holla@arm.com, liuyonglong@huawei.com, zhanjie9@hisilicon.com, "linux-acpi@vger.kernel.org" Subject: Re: [PATCH] cpufreq: CPPC: Resolve the large frequency discrepancy from cpuinfo_cur_freq Message-ID: References: <20231212072617.14756-1-lihuisong@huawei.com> <9428a1ed-ba4d-1fe6-63e8-11e152bf1f09@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240108_060313_823539_028092EE X-CRM114-Status: GOOD ( 58.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SGksCgpPbiBGcmlkYXkgMDUgSmFuIDIwMjQgYXQgMTU6MDQ6NDcgKCswODAwKSwgbGlodWlzb25n IChDKSB3cm90ZToKPiBIaSBWYW5zaGksCj4gCj4g5ZyoIDIwMjQvMS81IDg6NDgsIFZhbnNoaWRo YXIgS29uZGEg5YaZ6YGTOgo+ID4gT24gVGh1LCBKYW4gMDQsIDIwMjQgYXQgMDU6MzY6NTFQTSAr MDgwMCwgbGlodWlzb25nIChDKSB3cm90ZToKPiA+ID4gCj4gPiA+IOWcqCAyMDI0LzEvNCAxOjUz LCBJb25lbGEgVm9pbmVzY3Ug5YaZ6YGTOgo+ID4gPiA+IEhpLAo+ID4gPiA+IAo+ID4gPiA+IE9u IFR1ZXNkYXkgMTIgRGVjIDIwMjMgYXQgMTU6MjY6MTcgKCswODAwKSwgSHVpc29uZyBMaSB3cm90 ZToKPiA+ID4gPiA+IE1hbnkgZGV2ZWxvcGVycyBmb3VuZCB0aGF0IHRoZSBjcHUgY3VycmVudCBm cmVxdWVuY3kgaXMgZ3JlYXRlciB0aGFuCj4gPiA+ID4gPiB0aGUgbWF4aW11bSBmcmVxdWVuY3kg b2YgdGhlIHBsYXRmb3JtLCBwbGVhc2Ugc2VlIFsxXSwgWzJdIGFuZCBbM10uCj4gPiA+ID4gPiAK PiA+ID4gPiA+IEluIHRoZSBzY2VuYXJpb3Mgd2l0aCBoaWdoIG1lbW9yeSBhY2Nlc3MgcHJlc3N1 cmUsIHRoZSBwYXRjaCBbMV0gaGFzCj4gPiA+ID4gPiBwcm92ZWQgdGhlIHNpZ25pZmljYW50IGxh dGVuY3kgb2YgY3BjX3JlYWQoKSB3aGljaCBpcyB1c2VkIHRvIG9idGFpbgo+ID4gPiA+ID4gZGVs aXZlcmVkIGFuZCByZWZlcmVuY2UgcGVyZm9ybWFuY2UgY291bnRlciBjYXVzZSBhbiBhYnN1cmQg ZnJlcXVlbmN5Lgo+ID4gPiA+ID4gVGhlIHNhbXBsaW5nIGludGVydmFsIGZvciB0aGlzIGNvdW50 ZXJzIGlzIHZlcnkgY3JpdGljYWwgYW5kCj4gPiA+ID4gPiBpcyBleHBlY3RlZAo+ID4gPiA+ID4g dG8gYmUgZXF1YWwuIEhvd2V2ZXIsIHRoZSBkaWZmZXJlbnQgbGF0ZW5jeSBvZiBjcGNfcmVhZCgp IGhhcyBhIGRpcmVjdAo+ID4gPiA+ID4gaW1wYWN0IG9uIHRoZWlyIHNhbXBsaW5nIGludGVydmFs Lgo+ID4gPiA+ID4gCj4gPiA+ID4gV291bGQgdGhpcyBbMV0gYWx0ZXJuYXRpdmUgc29sdXRpb24g d29yayBmb3IgeW91Pwo+ID4gPiBJdCB3b3VsZCB3b3JrIGZvciBtZSBBRkFJQ1MuCj4gPiA+IEJl Y2F1c2UgdGhlICJhcmNoX2ZyZXFfc2NhbGUiIGlzIGFsc28gZnJvbSBBTVUgY29yZSBhbmQgY29u c3RhbnQKPiA+ID4gY291bnRlciwgYW5kIHJlYWQgdG9nZXRoZXIuCj4gPiA+IEJ1dCwgZnJvbSB0 aGVpciBkaXNjdXNzIGxpbmUsIGl0IHNlZW1zIHRoYXQgdGhlcmUgYXJlIHNvbWUgdHJpY2t5Cj4g PiA+IHBvaW50cyB0byBjbGFyaWZ5IG9yIGNvbnNpZGVyLgo+ID4gCj4gPiBJIHRoaW5rIHRoZSBj aGFuZ2VzIGluIFsxXSB3b3VsZCB3b3JrIGJldHRlciB3aGVuIENQVXMgbWF5IGJlIGlkbGUuIFdp dGgKPiA+IHRoaXMKPiA+IHBhdGNoIHdlIHdvdWxkIGhhdmUgdG8gd2FrZSBhbnkgY29yZSB0aGF0 IGlzIGluIGlkbGUgc3RhdGUgdG8gcmVhZCB0aGUKPiA+IEFNVQo+ID4gY291bnRlcnMuIFdvcnN0 IGNhc2UsIGlmIGNvcmUgMCBpcyB0cnlpbmcgdG8gcmVhZCB0aGUgQ1BVIGZyZXF1ZW5jeSBvZgo+ ID4gYWxsCj4gPiBjb3JlcywgaXQgbWF5IG5lZWQgdG8gd2FrZSB1cCBhbGwgdGhlIG90aGVyIGNv cmVzIHRvIHJlYWQgdGhlIEFNVQo+ID4gY291bnRlcnMuCj4gRnJvbSB0aGUgYXBwcm9hY2ggaW4g WzFdLCBpZiBhbGwgQ1BVcyAob25lIG9yIG1vcmUgY29yZXMpIHVuZGVyIG9uZSBwb2xpY3kKPiBh cmUgaWRsZSwgdGhleSBzdGlsbCBjYW5ub3QgYmUgb2J0YWluZWQgdGhlIENQVSBmcmVxdWVuY3ks IHJpZ2h0Pwo+IEluIHRoaXMgY2FzZSwgdGhlIFsxXSBBUEkgd2lsbCByZXR1cm4gMCBhbmQgaGF2 ZSB0byBiYWNrIHRvIGNhbGwKPiBjcHVmcmVxX2RyaXZlci0+Z2V0KCkgZm9yIGNwdWluZm9fY3Vy X2ZyZXEuCj4gVGhlbiB3ZSBzdGlsbCBuZWVkIHRvIGZhY2UgdGhlIGlzc3VlIHRoaXMgcGF0Y2gg bWVudGlvbmVkLgoKV2l0aCB0aGUgaW1wbGVtZW50YXRpb24gYXQgWzFdLCBhcmNoX2ZyZXFfZ2V0 X29uX2NwdSgpIHdpbGwgbm90IHJldHVybiAwCmZvciBpZGxlIENQVXMgYW5kIHRoZSBnZXQoKSBj YWxsYmFjayB3aWxsIG5vdCBiZSBjYWxsZWQgdG8gd2FrZSB1cCB0aGUKQ1BVcy4KCldvcnN0IGNh c2UsIGFyY2hfZnJlcV9nZXRfb25fY3B1KCkgd2lsbCByZXR1cm4gYSBmcmVxdWVuY3kgYmFzZWQg b24gdGhlCkFNVSBjb3VudGVyIHZhbHVlcyBvYnRhaW5lZCBvbiB0aGUgbGFzdCB0aWNrIG9uIHRo YXQgQ1BVLiBCdXQgaWYgdGhhdCBDUFUKaXMgbm90IGEgaG91c2VrZWVwaW5nIENQVSwgYSBob3Vz ZWtlZXBpbmcgQ1BVIGluIHRoZSBzYW1lIHBvbGljeSB3aWxsIGJlCnNlbGVjdGVkLCBhcyBpdCB3 b3VsZCBoYXZlIGhhZCBhIG1vcmUgcmVjZW50IHRpY2ssIGFuZCB0aGVyZWZvcmUgYSBtb3JlCnJl Y2VudCBmcmVxdWVuY3kgdmFsdWUgZm9yIHRoZSBkb21haW4uCgpJIHVuZGVyc3RhbmQgdGhhdCB0 aGUgZnJlcXVlbmN5IHJldHVybmVkIGhlcmUgd2lsbCBub3QgYmUgdXAgdG8gZGF0ZSwKYnV0IHRo ZXJlJ3Mgbm8gcHJvcGVyIGZyZXF1ZW5jeSBmZWVkYmFjayBmb3IgYW4gaWRsZSBDUFUuIElmIG9u ZSBvbmx5Cndha2VzIHVwIGEgQ1BVIHRvIHNhbXBsZSBjb3VudGVycywgYmVmb3JlIHRoZSBDUFUg Z29lcyBiYWNrIHRvIHNsZWVwLAp0aGUgb2J0YWluZWQgZnJlcXVlbmN5IGZlZWRiYWNrIGlzIG1l YW5pbmdsZXNzLgoKPiA+IEZvciBzeXN0ZW1zIHdpdGggMTI4IGNvcmVzIG9yIG1vcmUsIHRoaXMg Y291bGQgYmUgdmVyeSBleHBlbnNpdmUgYW5kCj4gPiBoYXBwZW4KPiA+IHZlcnkgZnJlcXVlbnRs eS4KPiA+IAo+ID4gQUZBSUNTLCB0aGUgYXBwcm9hY2ggaW4gWzFdIHdvdWxkIGF2b2lkIHRoaXMg Y29zdC4KPiBCdXQgdGhlIENQVSBmcmVxdWVuY3kgaXMganVzdCBhbiBhdmVyYWdlIHZhbHVlIGZv ciB0aGUgbGFzdCB0aWNrIHBlcmlvZAo+IGluc3RlYWQgb2YgdGhlIGN1cnJlbnQgb25lIHRoZSBD UFUgYWN0dWFsbHkgcnVucyBhdC4KPiBJbiBhZGRpdGlvbiwgdGhlcmUgYXJlIHNvbWUgY29uZGl0 aW9ucyB0byB1c2UgJ2FyY2hfZnJlcV9zY2FsZScgaW4gdGhpcwo+IGFwcHJvYWNoLgoKV2hhdCBh cmUgdGhlIGNvbmRpdGlvbnMgeW91IGFyZSByZWZlcnJpbmcgdG8/Cgo+IFNvIEknbSBub3Qgc3Vy ZSBpZiB0aGlzIGFwcHJvYWNoIGNhbiBlbnRpcmVseSBjb3ZlciB0aGUgZnJlcXVlbmN5Cj4gZGlz Y3JlcGFuY3kgaXNzdWUuCgpVbmZvcnR1bmF0ZWx5IHRoZXJlIGlzIG5vIHBlcmZlY3QgZnJlcXVl bmN5IGZlZWRiYWNrLiBCeSB0aGUgdGltZSB5b3UKb2JzZXJ2ZS91c2UgdGhlIHZhbHVlIG9mIHNj YWxpbmdfY3VyX2ZyZXEvY3B1aW5mb19jdXJfZnJlcSwgdGhlIGZyZXF1ZW5jeQpvZiB0aGUgQ1BV IG1pZ2h0IGhhdmUgYWxyZWFkeSBjaGFuZ2VkLiBUaGVyZWZvcmUsIGFuIGF2ZXJhZ2UgdmFsdWUg bWlnaHQKYmUgYSBiZXR0ZXIgaW5kaWNhdGlvbiBvZiB0aGUgcmVjZW50IHBlcmZvcm1hbmNlIGxl dmVsIG9mIGEgQ1BVLgoKV291bGQgeW91IGJlIGFibGUgdG8gdGVzdCBbMV0gb24geW91ciBwbGF0 Zm9ybSBhbmQgdXNlY2FzZT8KCk1hbnkgdGhhbmtzLApJb25lbGEuCgo+IAo+IC9IdWlzb25nCj4g Cj4gPiA+ID4gCj4gPiA+ID4gWzFdIGh0dHBzOi8vbG9yZS5rZXJuZWwub3JnL2xrbWwvMjAyMzEx MjcxNjA4MzguMTQwMzQwNC0xLWJlYXRhLm1pY2hhbHNrYUBhcm0uY29tLwo+ID4gPiA+IAo+ID4g PiA+IFRoYW5rcywKPiA+ID4gPiBJb25lbGEuCj4gPiA+ID4gCj4gPiA+ID4gPiBUaGlzIHBhdGNo IGFkZHMgYSBpbnRlcmZhY2UsIGNwY19yZWFkX2FyY2hfY291bnRlcnNfb25fY3B1LCB0byByZWFk Cj4gPiA+ID4gPiBkZWxpdmVyZWQgYW5kIHJlZmVyZW5jZSBwZXJmb3JtYW5jZSBjb3VudGVyIHRv Z2V0aGVyLiBBY2NvcmRpbmcgdG8gbXkKPiA+ID4gPiA+IHRlc3RbNF0sIHRoZSBkaXNjcmVwYW5j eSBvZiBjcHUgY3VycmVudCBmcmVxdWVuY3kgaW4gdGhlCj4gPiA+ID4gPiBzY2VuYXJpb3Mgd2l0 aAo+ID4gPiA+ID4gaGlnaCBtZW1vcnkgYWNjZXNzIHByZXNzdXJlIGlzIGxvd2VyIHRoYW4gMC4y JSBieSBzdHJlc3MtbmcKPiA+ID4gPiA+IGFwcGxpY2F0aW9uLgo+ID4gPiA+ID4gCj4gPiA+ID4g PiBbMV0gaHR0cHM6Ly9sb3JlLmtlcm5lbC5vcmcvYWxsLzIwMjMxMDI1MDkzODQ3LjM3NDAxMDQt NC16ZW5naGVuZzRAaHVhd2VpLmNvbS8KPiA+ID4gPiA+IFsyXSBodHRwczovL2xvcmUua2VybmVs Lm9yZy9hbGwvMjAyMzAzMjgxOTM4NDYuODc1Ny0xLXlhbmdAb3MuYW1wZXJlY29tcHV0aW5nLmNv bS8KPiA+ID4gPiA+IFszXQo+ID4gPiA+ID4gaHR0cHM6Ly9sb3JlLmtlcm5lbC5vcmcvYWxsLzIw MjMwNDE4MTEzNDU5LjEyODYwLTctc3VtaXRnQG52aWRpYS5jb20vCj4gPiA+ID4gPiAKPiA+ID4g PiA+IFs0XSBNeSBsb2NhbCB0ZXN0Ogo+ID4gPiA+ID4gVGhlIHRlc3RpbmcgcGxhdGZvcm0gZW5h YmxlIFNNVCBhbmQgaW5jbHVkZSAxMjggbG9naWNhbCBDUFUgaW4gdG90YWwsCj4gPiA+ID4gPiBh bmQgQ1BVIGJhc2UgZnJlcXVlbmN5IGlzIDIuN0dIei4gUmVhZGluZyAiY3B1aW5mb19jdXJfZnJl cSIgZm9yIGVhY2gKPiA+ID4gPiA+IHBoeXNpY2FsIGNvcmUgb24gcGxhdGZvcm0gZHVyaW5nIHRo ZSBoaWdoIG1lbW9yeSBhY2Nlc3MgcHJlc3N1cmUgZnJvbQo+ID4gPiA+ID4gc3RyZXNzLW5nLCBh bmQgdGhlIG91dHB1dCBpcyBhcyBmb2xsb3dzOgo+ID4gPiA+ID4gwqAgMDogMjY5OTEzM8KgwqDC oMKgIDI6IDI2OTk5NDLCoMKgwqDCoCA0OiAyNjk4MTg5wqDCoMKgwqAgNjogMjcwNDM0Nwo+ID4g PiA+ID4gwqAgODogMjcwNDAwOcKgwqDCoCAxMDogMjY5NjI3N8KgwqDCoCAxMjogMjcwMjAxNsKg wqDCoCAxNDogMjcwMTM4OAo+ID4gPiA+ID4gwqAxNjogMjcwMDM1OMKgwqDCoCAxODogMjY5Njc0 McKgwqDCoCAyMDogMjcwMDA5McKgwqDCoCAyMjogMjcwMDEyMgo+ID4gPiA+ID4gwqAyNDogMjcw MTcxM8KgwqDCoCAyNjogMjcwMjAyNcKgwqDCoCAyODogMjY5OTgxNsKgwqDCoCAzMDogMjcwMDEy MQo+ID4gPiA+ID4gwqAzMjogMjcwMDAwMMKgwqDCoCAzNDogMjY5OTc4OMKgwqDCoCAzNjogMjY5 ODg4NMKgwqDCoCAzODogMjY5OTEwOQo+ID4gPiA+ID4gwqA0MDogMjcwNDQ5NMKgwqDCoCA0Mjog MjY5ODM1MMKgwqDCoCA0NDogMjY5OTk5N8KgwqDCoCA0NjogMjcwMTAyMwo+ID4gPiA+ID4gwqA0 ODogMjcwMzQ0OMKgwqDCoCA1MDogMjY5OTUwMcKgwqDCoCA1MjogMjcwMDAwMMKgwqDCoCA1NDog MjY5OTk5OQo+ID4gPiA+ID4gwqA1NjogMjcwMjY0NcKgwqDCoCA1ODogMjY5NjkyM8KgwqDCoCA2 MDogMjY5NzcxOMKgwqDCoCA2MjogMjcwMDU0Nwo+ID4gPiA+ID4gwqA2NDogMjcwMDMxM8KgwqDC oCA2NjogMjcwMDAwMMKgwqDCoCA2ODogMjY5OTkwNMKgwqDCoCA3MDogMjY5OTI1OQo+ID4gPiA+ ID4gwqA3MjogMjY5OTUxMcKgwqDCoCA3NDogMjcwMDY0NMKgwqDCoCA3NjogMjcwMjIwMcKgwqDC oCA3ODogMjcwMDAwMAo+ID4gPiA+ID4gwqA4MDogMjcwMDc3NsKgwqDCoCA4MjogMjcwMDM2NMKg wqDCoCA4NDogMjcwMjY3NMKgwqDCoCA4NjogMjcwMDI1NQo+ID4gPiA+ID4gwqA4ODogMjY5OTg4 NsKgwqDCoCA5MDogMjcwMDM1OcKgwqDCoCA5MjogMjY5OTY2MsKgwqDCoCA5NDogMjY5NjE4OAo+ ID4gPiA+ID4gwqA5NjogMjcwNTQ1NMKgwqDCoCA5ODogMjY5OTI2MMKgwqAgMTAwOiAyNzAxMDk3 wqDCoCAxMDI6IDI2OTk2MzAKPiA+ID4gPiA+IDEwNDogMjcwMDQ2M8KgwqAgMTA2OiAyNjk4NDA4 wqDCoCAxMDg6IDI2OTc3NjbCoMKgIDExMDogMjcwMTE4MQo+ID4gPiA+ID4gMTEyOiAyNjk5MTY2 wqDCoCAxMTQ6IDI3MDE4MDTCoMKgIDExNjogMjcwMTkwN8KgwqAgMTE4OiAyNzAxOTczCj4gPiA+ ID4gPiAxMjA6IDI2OTk1ODTCoMKgIDEyMjogMjcwMDQ3NMKgwqAgMTI0OiAyNzAwNzY4wqDCoCAx MjY6IDI3MDE5NjMKPiA+ID4gPiA+IAo+ID4gPiA+ID4gU2lnbmVkLW9mZi1ieTogSHVpc29uZyBM aSA8bGlodWlzb25nQGh1YXdlaS5jb20+Cj4gPiA+ID4gPiAtLS0KPiA+ID4gPiA+IMKgYXJjaC9h cm02NC9rZXJuZWwvdG9wb2xvZ3kuYyB8IDQzCj4gPiA+ID4gPiArKysrKysrKysrKysrKysrKysr KysrKysrKysrKysrKysrLS0KPiA+ID4gPiA+IMKgZHJpdmVycy9hY3BpL2NwcGNfYWNwaS5jwqDC oMKgwqAgfCAyMiArKysrKysrKysrKysrKystLS0KPiA+ID4gPiA+IMKgaW5jbHVkZS9hY3BpL2Nw cGNfYWNwaS5owqDCoMKgwqAgfMKgIDUgKysrKysKPiA+ID4gPiA+IMKgMyBmaWxlcyBjaGFuZ2Vk LCA2NSBpbnNlcnRpb25zKCspLCA1IGRlbGV0aW9ucygtKQo+ID4gPiA+ID4gCj4gPiA+ID4gPiBk aWZmIC0tZ2l0IGEvYXJjaC9hcm02NC9rZXJuZWwvdG9wb2xvZ3kuYwo+ID4gPiA+ID4gYi9hcmNo L2FybTY0L2tlcm5lbC90b3BvbG9neS5jCj4gPiA+ID4gPiBpbmRleCA3ZDM3ZTQ1OGUyZjUuLmMz MTIyMTU0ZDczOCAxMDA2NDQKPiA+ID4gPiA+IC0tLSBhL2FyY2gvYXJtNjQva2VybmVsL3RvcG9s b2d5LmMKPiA+ID4gPiA+ICsrKyBiL2FyY2gvYXJtNjQva2VybmVsL3RvcG9sb2d5LmMKPiA+ID4g PiA+IEBAIC0yOTksNiArMjk5LDExIEBAIGNvcmVfaW5pdGNhbGwoaW5pdF9hbXVfZmllKTsKPiA+ ID4gPiA+IMKgI2lmZGVmIENPTkZJR19BQ1BJX0NQUENfTElCCj4gPiA+ID4gPiDCoCNpbmNsdWRl IDxhY3BpL2NwcGNfYWNwaS5oPgo+ID4gPiA+ID4gK3N0cnVjdCBhbXVfY291bnRlcnMgewo+ID4g PiA+ID4gK8KgwqDCoCB1NjQgY29yZWNudDsKPiA+ID4gPiA+ICvCoMKgwqAgdTY0IGNvbnN0Y250 Owo+ID4gPiA+ID4gK307Cj4gPiA+ID4gPiArCj4gPiA+ID4gPiDCoHN0YXRpYyB2b2lkIGNwdV9y ZWFkX2NvcmVjbnQodm9pZCAqdmFsKQo+ID4gPiA+ID4gwqB7Cj4gPiA+ID4gPiDCoMKgwqDCoCAv Kgo+ID4gPiA+ID4gQEAgLTMyMiw4ICszMjcsMjcgQEAgc3RhdGljIHZvaWQgY3B1X3JlYWRfY29u c3RjbnQodm9pZCAqdmFsKQo+ID4gPiA+ID4gwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCAw VUwgOiByZWFkX2NvbnN0Y250KCk7Cj4gPiA+ID4gPiDCoH0KPiA+ID4gPiA+ICtzdGF0aWMgdm9p ZCBjcHVfcmVhZF9hbXVfY291bnRlcnModm9pZCAqZGF0YSkKPiA+ID4gPiA+ICt7Cj4gPiA+ID4g PiArwqDCoMKgIHN0cnVjdCBhbXVfY291bnRlcnMgKmNudCA9IChzdHJ1Y3QgYW11X2NvdW50ZXJz ICopZGF0YTsKPiA+ID4gPiA+ICsKPiA+ID4gPiA+ICvCoMKgwqAgLyoKPiA+ID4gPiA+ICvCoMKg wqDCoCAqIFRoZSBydW5uaW5nIHRpbWUgb2YgdGhlIHRoaXNfY3B1X2hhc19jYXAoKSBtaWdodAo+ ID4gPiA+ID4gaGF2ZSBhIGNvdXBsZSBvZgo+ID4gPiA+ID4gK8KgwqDCoMKgICogbWljcm9zZWNv bmRzIGFuZCBpcyBzaWduaWZpY2FudGx5IGluY3JlYXNlZCB0byB0ZW5zCj4gPiA+ID4gPiBvZiBt aWNyb3NlY29uZHMuCj4gPiA+ID4gPiArwqDCoMKgwqAgKiBCdXQgQU1VIGNvcmUgYW5kIGNvbnN0 YW50IGNvdW50ZXIgbmVlZCB0byBiZSByZWFkCj4gPiA+ID4gPiB0b2dldGVyIHdpdGhvdXQgYW55 Cj4gPiA+ID4gPiArwqDCoMKgwqAgKiB0aW1lIGludGVydmFsIHRvIHJlZHVjZSB0aGUgY2FsY3Vs YXRpb24gZGlzY3JlcGFuY3kKPiA+ID4gPiA+IHVzaW5nIHRoaXMgY291bnRlcnMuCj4gPiA+ID4g PiArwqDCoMKgwqAgKi8KPiA+ID4gPiA+ICvCoMKgwqAgaWYgKHRoaXNfY3B1X2hhc19jYXAoQVJN NjRfV09SS0FST1VORF8yNDU3MTY4KSkgewo+ID4gPiA+ID4gK8KgwqDCoMKgwqDCoMKgIGNudC0+ Y29yZWNudCA9IHJlYWRfY29yZWNudCgpOwo+ID4gPiA+ID4gK8KgwqDCoMKgwqDCoMKgIGNudC0+ Y29uc3RjbnQgPSAwOwo+ID4gPiA+ID4gK8KgwqDCoCB9IGVsc2Ugewo+ID4gPiA+ID4gK8KgwqDC oMKgwqDCoMKgIGNudC0+Y29yZWNudCA9IHJlYWRfY29yZWNudCgpOwo+ID4gPiA+ID4gK8KgwqDC oMKgwqDCoMKgIGNudC0+Y29uc3RjbnQgPSByZWFkX2NvbnN0Y250KCk7Cj4gPiA+ID4gPiArwqDC oMKgIH0KPiA+ID4gPiA+ICt9Cj4gPiA+ID4gPiArCj4gPiA+ID4gPiDCoHN0YXRpYyBpbmxpbmUK PiA+ID4gPiA+IC1pbnQgY291bnRlcnNfcmVhZF9vbl9jcHUoaW50IGNwdSwgc21wX2NhbGxfZnVu Y190IGZ1bmMsIHU2NCAqdmFsKQo+ID4gPiA+ID4gK2ludCBjb3VudGVyc19yZWFkX29uX2NwdShp bnQgY3B1LCBzbXBfY2FsbF9mdW5jX3QgZnVuYywgdm9pZCAqZGF0YSkKPiA+ID4gPiA+IMKgewo+ ID4gPiA+ID4gwqDCoMKgwqAgLyoKPiA+ID4gPiA+IMKgwqDCoMKgwqAgKiBBYm9ydCBjYWxsIG9u IGNvdW50ZXJsZXNzIENQVSBvciB3aGVuIGludGVycnVwdHMgYXJlCj4gPiA+ID4gPiBAQCAtMzM1 LDcgKzM1OSw3IEBAIGludCBjb3VudGVyc19yZWFkX29uX2NwdShpbnQgY3B1LAo+ID4gPiA+ID4g c21wX2NhbGxfZnVuY190IGZ1bmMsIHU2NCAqdmFsKQo+ID4gPiA+ID4gwqDCoMKgwqAgaWYgKFdB Uk5fT05fT05DRShpcnFzX2Rpc2FibGVkKCkpKQo+ID4gPiA+ID4gwqDCoMKgwqDCoMKgwqDCoCBy ZXR1cm4gLUVQRVJNOwo+ID4gPiA+ID4gLcKgwqDCoCBzbXBfY2FsbF9mdW5jdGlvbl9zaW5nbGUo Y3B1LCBmdW5jLCB2YWwsIDEpOwo+ID4gPiA+ID4gK8KgwqDCoCBzbXBfY2FsbF9mdW5jdGlvbl9z aW5nbGUoY3B1LCBmdW5jLCBkYXRhLCAxKTsKPiA+ID4gPiA+IMKgwqDCoMKgIHJldHVybiAwOwo+ ID4gPiA+ID4gwqB9Cj4gPiA+ID4gPiBAQCAtMzY0LDYgKzM4OCwyMSBAQCBib29sIGNwY19mZmhf c3VwcG9ydGVkKHZvaWQpCj4gPiA+ID4gPiDCoMKgwqDCoCByZXR1cm4gdHJ1ZTsKPiA+ID4gPiA+ IMKgfQo+ID4gPiA+ID4gK2ludCBjcGNfcmVhZF9hcmNoX2NvdW50ZXJzX29uX2NwdShpbnQgY3B1 LCB1NjQgKmRlbGl2ZXJlZCwKPiA+ID4gPiA+IHU2NCAqcmVmZXJlbmNlKQo+ID4gPiA+ID4gK3sK PiA+ID4gPiA+ICvCoMKgwqAgc3RydWN0IGFtdV9jb3VudGVycyBjbnRzID0gezB9Owo+ID4gPiA+ ID4gK8KgwqDCoCBpbnQgcmV0Owo+ID4gPiA+ID4gKwo+ID4gPiA+ID4gK8KgwqDCoCByZXQgPSBj b3VudGVyc19yZWFkX29uX2NwdShjcHUsIGNwdV9yZWFkX2FtdV9jb3VudGVycywgJmNudHMpOwo+ ID4gPiA+ID4gK8KgwqDCoCBpZiAocmV0KQo+ID4gPiA+ID4gK8KgwqDCoMKgwqDCoMKgIHJldHVy biByZXQ7Cj4gPiA+ID4gPiArCj4gPiA+ID4gPiArwqDCoMKgICpkZWxpdmVyZWQgPSBjbnRzLmNv cmVjbnQ7Cj4gPiA+ID4gPiArwqDCoMKgICpyZWZlcmVuY2UgPSBjbnRzLmNvbnN0Y250Owo+ID4g PiA+ID4gKwo+ID4gPiA+ID4gK8KgwqDCoCByZXR1cm4gMDsKPiA+ID4gPiA+ICt9Cj4gPiA+ID4g PiArCj4gPiA+ID4gPiDCoGludCBjcGNfcmVhZF9mZmgoaW50IGNwdSwgc3RydWN0IGNwY19yZWcg KnJlZywgdTY0ICp2YWwpCj4gPiA+ID4gPiDCoHsKPiA+ID4gPiA+IMKgwqDCoMKgIGludCByZXQg PSAtRU9QTk9UU1VQUDsKPiA+ID4gPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2FjcGkvY3BwY19h Y3BpLmMgYi9kcml2ZXJzL2FjcGkvY3BwY19hY3BpLmMKPiA+ID4gPiA+IGluZGV4IDdmZjI2OWE3 OGMyMC4uZjMwM2ZhYmQ3Y2ZlIDEwMDY0NAo+ID4gPiA+ID4gLS0tIGEvZHJpdmVycy9hY3BpL2Nw cGNfYWNwaS5jCj4gPiA+ID4gPiArKysgYi9kcml2ZXJzL2FjcGkvY3BwY19hY3BpLmMKPiA+ID4g PiA+IEBAIC0xMjk5LDYgKzEyOTksMTEgQEAgYm9vbCBjcHBjX3BlcmZfY3Ryc19pbl9wY2Modm9p ZCkKPiA+ID4gPiA+IMKgfQo+ID4gPiA+ID4gwqBFWFBPUlRfU1lNQk9MX0dQTChjcHBjX3BlcmZf Y3Ryc19pbl9wY2MpOwo+ID4gPiA+ID4gK2ludCBfX3dlYWsgY3BjX3JlYWRfYXJjaF9jb3VudGVy c19vbl9jcHUoaW50IGNwdSwgdTY0Cj4gPiA+ID4gPiAqZGVsaXZlcmVkLCB1NjQgKnJlZmVyZW5j ZSkKPiA+ID4gPiA+ICt7Cj4gPiA+ID4gPiArwqDCoMKgIHJldHVybiAwOwo+ID4gPiA+ID4gK30K PiA+ID4gPiA+ICsKPiA+ID4gPiA+IMKgLyoqCj4gPiA+ID4gPiDCoCAqIGNwcGNfZ2V0X3BlcmZf Y3RycyAtIFJlYWQgYSBDUFUncyBwZXJmb3JtYW5jZSBmZWVkYmFjayBjb3VudGVycy4KPiA+ID4g PiA+IMKgICogQGNwdW51bTogQ1BVIGZyb20gd2hpY2ggdG8gcmVhZCBjb3VudGVycy4KPiA+ID4g PiA+IEBAIC0xMzEzLDcgKzEzMTgsOCBAQCBpbnQgY3BwY19nZXRfcGVyZl9jdHJzKGludCBjcHVu dW0sCj4gPiA+ID4gPiBzdHJ1Y3QgY3BwY19wZXJmX2ZiX2N0cnMgKnBlcmZfZmJfY3RycykKPiA+ ID4gPiA+IMKgwqDCoMKgwqDCoMKgwqAgKnJlZl9wZXJmX3JlZywgKmN0cl93cmFwX3JlZzsKPiA+ ID4gPiA+IMKgwqDCoMKgIGludCBwY2Nfc3NfaWQgPSBwZXJfY3B1KGNwdV9wY2Nfc3Vic3BhY2Vf aWR4LCBjcHVudW0pOwo+ID4gPiA+ID4gwqDCoMKgwqAgc3RydWN0IGNwcGNfcGNjX2RhdGEgKnBj Y19zc19kYXRhID0gTlVMTDsKPiA+ID4gPiA+IC3CoMKgwqAgdTY0IGRlbGl2ZXJlZCwgcmVmZXJl bmNlLCByZWZfcGVyZiwgY3RyX3dyYXBfdGltZTsKPiA+ID4gPiA+ICvCoMKgwqAgdTY0IGRlbGl2 ZXJlZCA9IDAsIHJlZmVyZW5jZSA9IDA7Cj4gPiA+ID4gPiArwqDCoMKgIHU2NCByZWZfcGVyZiwg Y3RyX3dyYXBfdGltZTsKPiA+ID4gPiA+IMKgwqDCoMKgIGludCByZXQgPSAwLCByZWdzX2luX3Bj YyA9IDA7Cj4gPiA+ID4gPiDCoMKgwqDCoCBpZiAoIWNwY19kZXNjKSB7Cj4gPiA+ID4gPiBAQCAt MTM1MCw4ICsxMzU2LDE4IEBAIGludCBjcHBjX2dldF9wZXJmX2N0cnMoaW50IGNwdW51bSwKPiA+ ID4gPiA+IHN0cnVjdCBjcHBjX3BlcmZfZmJfY3RycyAqcGVyZl9mYl9jdHJzKQo+ID4gPiA+ID4g wqDCoMKgwqDCoMKgwqDCoCB9Cj4gPiA+ID4gPiDCoMKgwqDCoCB9Cj4gPiA+ID4gPiAtwqDCoMKg IGNwY19yZWFkKGNwdW51bSwgZGVsaXZlcmVkX3JlZywgJmRlbGl2ZXJlZCk7Cj4gPiA+ID4gPiAt wqDCoMKgIGNwY19yZWFkKGNwdW51bSwgcmVmZXJlbmNlX3JlZywgJnJlZmVyZW5jZSk7Cj4gPiA+ ID4gPiArwqDCoMKgIGlmIChjcGNfZmZoX3N1cHBvcnRlZCgpKSB7Cj4gPiA+ID4gPiArwqDCoMKg wqDCoMKgwqAgcmV0ID0gY3BjX3JlYWRfYXJjaF9jb3VudGVyc19vbl9jcHUoY3B1bnVtLAo+ID4g PiA+ID4gJmRlbGl2ZXJlZCwgJnJlZmVyZW5jZSk7Cj4gPiA+ID4gPiArwqDCoMKgwqDCoMKgwqAg aWYgKHJldCkgewo+ID4gPiA+ID4gK8KgwqDCoMKgwqDCoMKgwqDCoMKgwqAgcHJfZGVidWcoInJl YWQgYXJjaCBjb3VudGVycyBmYWlsZWQsIHJldD0lZC5cbiIsIHJldCk7Cj4gPiA+ID4gPiArwqDC oMKgwqDCoMKgwqDCoMKgwqDCoCByZXQgPSAwOwo+ID4gPiA+ID4gK8KgwqDCoMKgwqDCoMKgIH0K PiA+ID4gPiA+ICvCoMKgwqAgfQo+ID4gPiA+ID4gK8KgwqDCoCBpZiAoIWRlbGl2ZXJlZCB8fCAh cmVmZXJlbmNlKSB7Cj4gPiA+ID4gPiArwqDCoMKgwqDCoMKgwqAgY3BjX3JlYWQoY3B1bnVtLCBk ZWxpdmVyZWRfcmVnLCAmZGVsaXZlcmVkKTsKPiA+ID4gPiA+ICvCoMKgwqDCoMKgwqDCoCBjcGNf cmVhZChjcHVudW0sIHJlZmVyZW5jZV9yZWcsICZyZWZlcmVuY2UpOwo+ID4gPiA+ID4gK8KgwqDC oCB9Cj4gPiA+ID4gPiArCj4gPiA+ID4gPiDCoMKgwqDCoCBjcGNfcmVhZChjcHVudW0sIHJlZl9w ZXJmX3JlZywgJnJlZl9wZXJmKTsKPiA+ID4gPiA+IMKgwqDCoMKgIC8qCj4gPiA+ID4gPiBkaWZm IC0tZ2l0IGEvaW5jbHVkZS9hY3BpL2NwcGNfYWNwaS5oIGIvaW5jbHVkZS9hY3BpL2NwcGNfYWNw aS5oCj4gPiA+ID4gPiBpbmRleCA2MTI2Yzk3N2VjZTAuLjA3ZDRmZDgyZDQ5OSAxMDA2NDQKPiA+ ID4gPiA+IC0tLSBhL2luY2x1ZGUvYWNwaS9jcHBjX2FjcGkuaAo+ID4gPiA+ID4gKysrIGIvaW5j bHVkZS9hY3BpL2NwcGNfYWNwaS5oCj4gPiA+ID4gPiBAQCAtMTUyLDYgKzE1Miw3IEBAIGV4dGVy biBib29sIGNwY19mZmhfc3VwcG9ydGVkKHZvaWQpOwo+ID4gPiA+ID4gwqBleHRlcm4gYm9vbCBj cGNfc3VwcG9ydGVkX2J5X2NwdSh2b2lkKTsKPiA+ID4gPiA+IMKgZXh0ZXJuIGludCBjcGNfcmVh ZF9mZmgoaW50IGNwdW51bSwgc3RydWN0IGNwY19yZWcgKnJlZywgdTY0ICp2YWwpOwo+ID4gPiA+ ID4gwqBleHRlcm4gaW50IGNwY193cml0ZV9mZmgoaW50IGNwdW51bSwgc3RydWN0IGNwY19yZWcg KnJlZywgdTY0IHZhbCk7Cj4gPiA+ID4gPiArZXh0ZXJuIGludCBjcGNfcmVhZF9hcmNoX2NvdW50 ZXJzX29uX2NwdShpbnQgY3B1LCB1NjQKPiA+ID4gPiA+ICpkZWxpdmVyZWQsIHU2NCAqcmVmZXJl bmNlKTsKPiA+ID4gPiA+IMKgZXh0ZXJuIGludCBjcHBjX2dldF9lcHBfcGVyZihpbnQgY3B1bnVt LCB1NjQgKmVwcF9wZXJmKTsKPiA+ID4gPiA+IMKgZXh0ZXJuIGludCBjcHBjX3NldF9lcHBfcGVy ZihpbnQgY3B1LCBzdHJ1Y3QKPiA+ID4gPiA+IGNwcGNfcGVyZl9jdHJscyAqcGVyZl9jdHJscywg Ym9vbCBlbmFibGUpOwo+ID4gPiA+ID4gwqBleHRlcm4gaW50IGNwcGNfZ2V0X2F1dG9fc2VsX2Nh cHMoaW50IGNwdW51bSwgc3RydWN0Cj4gPiA+ID4gPiBjcHBjX3BlcmZfY2FwcyAqcGVyZl9jYXBz KTsKPiA+ID4gPiA+IEBAIC0yMDksNiArMjEwLDEwIEBAIHN0YXRpYyBpbmxpbmUgaW50IGNwY193 cml0ZV9mZmgoaW50Cj4gPiA+ID4gPiBjcHVudW0sIHN0cnVjdCBjcGNfcmVnICpyZWcsIHU2NCB2 YWwpCj4gPiA+ID4gPiDCoHsKPiA+ID4gPiA+IMKgwqDCoMKgIHJldHVybiAtRU5PVFNVUFA7Cj4g PiA+ID4gPiDCoH0KPiA+ID4gPiA+ICtzdGF0aWMgaW5saW5lIGludCBjcGNfcmVhZF9hcmNoX2Nv dW50ZXJzX29uX2NwdShpbnQgY3B1LAo+ID4gPiA+ID4gdTY0ICpkZWxpdmVyZWQsIHU2NCAqcmVm ZXJlbmNlKQo+ID4gPiA+ID4gK3sKPiA+ID4gPiA+ICvCoMKgwqAgcmV0dXJuIC1FT1BOT1RTVVBQ Owo+ID4gPiA+ID4gK30KPiA+ID4gPiA+IMKgc3RhdGljIGlubGluZSBpbnQgY3BwY19zZXRfZXBw X3BlcmYoaW50IGNwdSwgc3RydWN0Cj4gPiA+ID4gPiBjcHBjX3BlcmZfY3RybHMgKnBlcmZfY3Ry bHMsIGJvb2wgZW5hYmxlKQo+ID4gPiA+ID4gwqB7Cj4gPiA+ID4gPiDCoMKgwqDCoCByZXR1cm4g LUVOT1RTVVBQOwo+ID4gPiA+ID4gLS0gCj4gPiA+ID4gPiAyLjMzLjAKPiA+ID4gPiA+IAo+ID4g PiA+IC4KPiA+ID4gCj4gPiA+IF9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fCj4gPiA+IGxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBsaXN0Cj4gPiA+IGxpbnV4 LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZwo+ID4gPiBodHRwOi8vbGlzdHMuaW5mcmFk ZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LWFybS1rZXJuZWwKPiA+IAo+ID4gLgoKX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtl cm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0 dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5l bAo=