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From: Oliver Upton <oliver.upton@linux.dev>
To: Marc Zyngier <maz@kernel.org>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>
Subject: Re: [PATCH v2 3/6] KVM: arm64: Allow userspace to limit the number of PMU counters for EL2 VMs
Date: Wed, 9 Apr 2025 13:25:19 -0700	[thread overview]
Message-ID: <Z_bXr5izZdn93ryv@linux.dev> (raw)
In-Reply-To: <20250409160106.6445-4-maz@kernel.org>

On Wed, Apr 09, 2025 at 05:01:03PM +0100, Marc Zyngier wrote:
> As long as we had purely EL1 VMs, we could easily update the number
> of guest-visible counters by letting userspace write to PMCR_EL0.N.
> 
> With VMs started at EL2, PMCR_EL1.N only reflects MDCR_EL2.HPMN,
> and we don't have a good way to limit it.
> 
> For this purpose, introduce a new PMUv3 attribute that allows
> limiting the maximum number of counters. This requires the explicit
> selection of a PMU.
> 
> Suggested-by: Oliver Upton <oliver.upton@linux.dev>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
>  Documentation/virt/kvm/devices/vcpu.rst | 24 ++++++++++++++++++++++++
>  arch/arm64/include/uapi/asm/kvm.h       |  9 +++++----
>  arch/arm64/kvm/pmu-emul.c               | 24 ++++++++++++++++++++++++
>  3 files changed, 53 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/virt/kvm/devices/vcpu.rst b/Documentation/virt/kvm/devices/vcpu.rst
> index 31a9576c07afa..6eef154a2e396 100644
> --- a/Documentation/virt/kvm/devices/vcpu.rst
> +++ b/Documentation/virt/kvm/devices/vcpu.rst
> @@ -137,6 +137,30 @@ exit_reason = KVM_EXIT_FAIL_ENTRY and populate the fail_entry struct by setting
>  hardare_entry_failure_reason field to KVM_EXIT_FAIL_ENTRY_CPU_UNSUPPORTED and
>  the cpu field to the processor id.
>  
> +1.5 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_SET_PMCR_N

Similar to my comment on the kvm_arch field, this should be renamed to
something other than PMCR_N.

Otherwise the implementation of the ioctl itself LGTM.

> +---------------------------------------------
> +
> +:Parameters: in kvm_device_attr.addr the address to an unsigned int
> +	     representing the maximum value taken by PMCR_EL0.N
> +
> +:Returns:
> +
> +	 =======  ====================================================
> +	 -EBUSY   PMUv3 already initialized, a VCPU has already run or
> +                  an event filter has already been set
> +	 -EFAULT  Error accessing the value pointed to by addr
> +	 -ENODEV  PMUv3 not supported or GIC not initialized
> +	 -EINVAL  No PMUv3 explicitly selected, or value of N out of
> +	 	  range
> +	 =======  ====================================================
> +
> +Update the maximum value allowed in PMCR_EL0.N, defining the number of
> +counters visible to the guest.

Set the number of implemented event counters in the vPMU

Thanks,
Oliver

  reply	other threads:[~2025-04-09 20:25 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-09 16:01 [PATCH v2 0/6] KVM: arm64: EL2 PMU handling fixes Marc Zyngier
2025-04-09 16:01 ` [PATCH v2 1/6] KVM: arm64: Fix MDCR_EL2.HPMN reset value Marc Zyngier
2025-04-09 20:21   ` Oliver Upton
2025-04-10 10:54     ` Marc Zyngier
2025-04-10 17:38       ` Oliver Upton
2025-04-09 16:01 ` [PATCH v2 2/6] KVM: arm64: Contextualise the handling of PMCR_EL0.P writes Marc Zyngier
2025-04-09 16:01 ` [PATCH v2 3/6] KVM: arm64: Allow userspace to limit the number of PMU counters for EL2 VMs Marc Zyngier
2025-04-09 20:25   ` Oliver Upton [this message]
2025-04-09 16:01 ` [PATCH v2 4/6] KVM: arm64: Don't let userspace write to PMCR_EL0.N when the vcpu has EL2 Marc Zyngier
2025-04-09 16:01 ` [PATCH v2 5/6] KVM: arm64: Handle out-of-bound write to HDCR_EL2.HPMN Marc Zyngier
2025-04-09 20:29   ` Oliver Upton
2025-04-09 16:01 ` [PATCH v2 6/6] KVM: arm64: Let kvm_vcpu_read_pmcr() return an EL-dependent value for PMCR_EL0.N Marc Zyngier
2025-04-09 20:31 ` [PATCH v2 0/6] KVM: arm64: EL2 PMU handling fixes Oliver Upton
2025-04-11 12:00   ` Marc Zyngier

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