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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?jmg4JJ7d+Lytr1eLmdmGt+/107dnGtghJTswyf68cTH4fey3aFY5ODU2KWzS?= =?us-ascii?Q?6hvcnhsJmRfGhhmVPLqDjAwgJjBFpBK5zK0usIPorn8CeI5fshMK32Xdt6EC?= =?us-ascii?Q?fK/Xo0nB/VvAs7g6gpW9u3IAV8z++YtewnMJn0Bx6LkMcVIoo9/JJmR83uUW?= =?us-ascii?Q?is6oNNHSrDounLF/XnxgjFwlH9qJL1wPWx7FOiNOEwhe+95kd8w8d15noSPp?= =?us-ascii?Q?vDUxXXKcgABCGxCA7708nc7IbhGWjqQ+z3zAbJ/CD67T9k9izl6/ir0H5Fds?= =?us-ascii?Q?4S8tiG4ztovD18EQBF2Rfzb8c1VLCXPVr0yxze9oBEHVHmDprcrbQIzsPNHO?= =?us-ascii?Q?0T1/Vj5exlDSrMzmYQiS8gRv3vbh6asHEjU7iX8UlVNcq7R6HOB8DlKoYtbO?= =?us-ascii?Q?jG9sXGyDeN/IKLEa/rgeDvQ7KHEDTO2ZnEvDks0yhV2Btq8BR0G+d7f6uNkw?= =?us-ascii?Q?FC9JqMreJB6sj+4uFDWFeQwwmk0f7rd0nztrqetgsfLbxRk5zA5JHrRdXbcv?= =?us-ascii?Q?+7JKdPjYbDud9wrEpc1F5HAsNBccYc8Kesqg+HOJjp0BHeOGXrBvphQ6taqb?= =?us-ascii?Q?Fb+JZnbtBC9GfCGilc4wyhl7E1FkCNrumQwS3b6xqsHd4o7ZDes/wIOtjMg7?= =?us-ascii?Q?+acm8xRXRcV567ZX+DjKK/2IXQjJqQqKsQHr+xkfTj4wTA0vhXLToou4L9at?= =?us-ascii?Q?WSmUn7l4FHAyByCK4WPaMhPz+yn+1cieIh7tzpwXYACGH5P/+voHgBmCms4g?= =?us-ascii?Q?blS2VZ5IX2m4mc7pcu5xzzidgYQ6bSOAhji8rz2c/t0pRlvb/ylV9Aqig4nP?= =?us-ascii?Q?KT159BIhJeAewkGds8fYks7y1Gv2FCXdpWqLVI7w/mTGh2V11NPtxuCYnTeG?= =?us-ascii?Q?fOAy7mlZNssdVng12Htwo4rghBhTpGfB9YAIKDO90Oj+5a5gfKpeS+H8viA4?= =?us-ascii?Q?WemrJmsTMaMhiC0PNG8ZmIjpKpIquRtofxWsqmEYvPSY5pSbxA1JQxYs47WT?= =?us-ascii?Q?5875b9tdtbMXVSYL4n51mAOGC/sG7HyInkO9V5spdBqDjRcjoJLVidYM5pM2?= =?us-ascii?Q?hfTE/gJzamAAb2DTyb2QA15+qZPQLuok/De31i2sCSQt3fuQXwJqxX23nMHm?= =?us-ascii?Q?BfDwW6ayLEmI+vj9OmpAtq7EM+xaAs+OroE63808XVBCcc8otFzphOf5TX2x?= =?us-ascii?Q?2Y6KB0PegxSbVSePaVfIDSZdgkvFbjqRAJrekhY9MXiMtnghvGBslQ+PzXPF?= =?us-ascii?Q?P/D6QVfhA6mNv+VKGWBJDyjt0hcccJA30JxQz+koGgsba3fTUU2IjPajYr5T?= =?us-ascii?Q?l2/+qy0Nk1rXD8cb7mbPc93MKeKGBPdCEmH+IZooEwTAj1WtwCmYSiR0KnHz?= =?us-ascii?Q?srmEU/LT6hhRiQGjqt24ld4ZPgUwoMzEJ/iBZ3Frt6m3wCW0Q+gZJr5i4zt+?= =?us-ascii?Q?DSptOsTiQP1hSsPp/L5BZhjam8wtQlwCx5QUhV8TcCbVY/L6Fg4fW4Sp4F0o?= =?us-ascii?Q?Mh/uDJ/7x1NuWEggh3RDUup9kDjeT5o+35R/wkDsFvQ5pGW4iEuErxKLVJ12?= =?us-ascii?Q?CNoPFs4mRssq+Pf7uGFt/OQTARpp/XcadfQ4wmjp4j1sUk5cHaU7o4be+7zn?= =?us-ascii?Q?Ok5wObRmnjgdXH+0EUlu70E=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 57cc4e02-e493-4416-edae-08dc13a5f9e1 X-MS-Exchange-CrossTenant-AuthSource: DM4PR11MB5971.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jan 2024 19:37:56.3765 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xDhyPVFGjv9+j7NkLrZ6lSOPg/mnTQeagPkTWOa56nUlrNU1BCwBLyGyDjBIYWcfp6lKb79COrXOi96IxsQkIfjtGNukE7m7OWQFHa+rLkE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR11MB5401 X-OriginatorOrg: intel.com X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, Jan 12, 2024 at 12:17:25PM +0200, Jani Nikula wrote: > On Thu, 11 Jan 2024, Radhakrishna Sripada wrote: > > On Thu, Jan 11, 2024 at 07:21:17PM +0200, Jani Nikula wrote: > >> Add a function to check the opregion ASLE presence instead of accessing > >> the opregion structures directly. > >> > >> Reorder the checks in i915_has_asle() to avoid the function call if > >> possible. > >> > >> Cc: Radhakrishna Sripada > >> Signed-off-by: Jani Nikula > >> --- > >> drivers/gpu/drm/i915/display/intel_display_irq.c | 6 +++--- > >> drivers/gpu/drm/i915/display/intel_opregion.c | 5 +++++ > >> drivers/gpu/drm/i915/display/intel_opregion.h | 6 ++++++ > >> 3 files changed, 14 insertions(+), 3 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c > >> index 99843883cef7..f846c5b108b5 100644 > >> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c > >> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c > >> @@ -266,12 +266,12 @@ void i915_disable_pipestat(struct drm_i915_private *dev_priv, > >> intel_uncore_posting_read(&dev_priv->uncore, reg); > >> } > >> > >> -static bool i915_has_asle(struct drm_i915_private *dev_priv) > >> +static bool i915_has_asle(struct drm_i915_private *i915) > > Why not move this to intel_opregion.c and export it instead of > > intel_opregion_asle_present ? > > I'm trying to be conscious of the possible performance impact of making > calls from the irq code just to find there's nothing to do. Makes sense. > > >> { > >> - if (!dev_priv->display.opregion.asle) > >> + if (!IS_PINEVIEW(i915) && !IS_MOBILE(i915)) > > Can we extend this check to dgfx as well? > > Extend how? This will return early for everything after IVB. The name of the function is bit misleading as looking at Opregion code and the spec beyond IVB, asle aka Mailbox 3 is present, just that it is not used for reading pipestat. It is used to store rvda from where VBT is read. Extension is not required for this purpose. Might want to clear that unless I misunderstood the purpose, either way Reviewed-by: Radhakrishna Sripada > > BR, > Jani. > > > > > -Radhakrishna(RK) Sripada > > > >> return false; > >> > >> - return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); > >> + return intel_opregion_asle_present(i915); > >> } > >> > >> /** > >> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c > >> index 8b9e820971cb..26aacb01f9ec 100644 > >> --- a/drivers/gpu/drm/i915/display/intel_opregion.c > >> +++ b/drivers/gpu/drm/i915/display/intel_opregion.c > >> @@ -632,6 +632,11 @@ static void asle_work(struct work_struct *work) > >> asle->aslc = aslc_stat; > >> } > >> > >> +bool intel_opregion_asle_present(struct drm_i915_private *i915) > >> +{ > >> + return i915->display.opregion.asle; > >> +} > >> + > >> void intel_opregion_asle_intr(struct drm_i915_private *dev_priv) > >> { > >> if (dev_priv->display.opregion.asle) > >> diff --git a/drivers/gpu/drm/i915/display/intel_opregion.h b/drivers/gpu/drm/i915/display/intel_opregion.h > >> index 9efadfb72584..d084b30e8703 100644 > >> --- a/drivers/gpu/drm/i915/display/intel_opregion.h > >> +++ b/drivers/gpu/drm/i915/display/intel_opregion.h > >> @@ -69,6 +69,7 @@ void intel_opregion_resume(struct drm_i915_private *dev_priv); > >> void intel_opregion_suspend(struct drm_i915_private *dev_priv, > >> pci_power_t state); > >> > >> +bool intel_opregion_asle_present(struct drm_i915_private *i915); > >> void intel_opregion_asle_intr(struct drm_i915_private *dev_priv); > >> int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, > >> bool enable); > >> @@ -111,6 +112,11 @@ static inline void intel_opregion_suspend(struct drm_i915_private *dev_priv, > >> { > >> } > >> > >> +static inline bool intel_opregion_asle_present(struct drm_i915_private *i915) > >> +{ > >> + return false; > >> +} > >> + > >> static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv) > >> { > >> } > >> -- > >> 2.39.2 > >> > > -- > Jani Nikula, Intel