From: Matt Atwood <matthew.s.atwood@intel.com>
To: Haridhar Kalvala <haridhar.kalvala@intel.com>,
<intel-gfx@lists.freedesktop.org>
Cc: intel-gfx@lists.freedesktop.org, matthew.d.roper@intel.com
Subject: Re: [PATCH v1 3/3] drm/i915/xelpg: Extend some workarounds/tuning to gfx version 12.74
Date: Thu, 18 Jan 2024 15:22:50 -0800 [thread overview]
Message-ID: <ZamyyoqLPEGNTHNw@msatwood-mobl> (raw)
In-Reply-To: <20240108122738.14399-4-haridhar.kalvala@intel.com>
On Mon, Jan 08, 2024 at 05:57:38PM +0530, Haridhar Kalvala wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
>
> Some of our existing Xe_LPG workarounds and tuning are also applicable
> to the version 12.74 variant. Extend the condition bounds accordingly.
> Also fix the comment on Wa_14018575942 while we're at it.
>
> v2: Extend some more workarounds (Harish)
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
> Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 +++++++++++++--------
> drivers/gpu/drm/i915/i915_perf.c | 2 +-
> 3 files changed, 18 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 86a04afff64b..e1bf13e3d307 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -226,7 +226,7 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs)
> static int mtl_dummy_pipe_control(struct i915_request *rq)
> {
> /* Wa_14016712196 */
> - if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 71)) ||
> + if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) ||
> IS_DG2(rq->i915)) {
> u32 *cs;
>
> @@ -822,7 +822,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> flags |= PIPE_CONTROL_FLUSH_L3;
>
> /* Wa_14016712196 */
> - if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))
> + if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915))
> /* dummy PIPE_CONTROL + depth flush */
> cs = gen12_emit_pipe_control(cs, 0,
> PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 3eacbc50caf8..72dac27d9332 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -789,8 +789,13 @@ static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>
> dg2_ctx_gt_tuning_init(engine, wal);
>
> - if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
> - IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
> + /*
> + * Due to Wa_16014892111, the DRAW_WATERMARK tuning must be done in
> + * gen12_emit_indirect_ctx_rcs() rather than here on some early
> + * steppings.
> + */
> + if (!(IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> + IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)))
> wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
> }
>
> @@ -908,7 +913,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> if (engine->class != RENDER_CLASS)
> goto done;
>
> - if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
> + if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
> xelpg_ctx_workarounds_init(engine, wal);
> else if (IS_PONTEVECCHIO(i915))
> ; /* noop; none at this time */
> @@ -1643,7 +1648,7 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> static void
> xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> - /* Wa_14018778641 / Wa_18018781329 */
> + /* Wa_14018575942 / Wa_18018781329 */
> wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
>
> /* Wa_22016670082 */
> @@ -1710,7 +1715,7 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> */
> static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
> {
> - if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
> + if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) {
> wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
> wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
> }
> @@ -1743,7 +1748,7 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
> return;
> }
>
> - if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
> + if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
> xelpg_gt_workarounds_init(gt, wal);
> else if (IS_PONTEVECCHIO(i915))
> pvc_gt_workarounds_init(gt, wal);
> @@ -2216,7 +2221,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>
> if (engine->gt->type == GT_MEDIA)
> ; /* none yet */
> - else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
> + else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))
> xelpg_whitelist_build(engine);
> else if (IS_PONTEVECCHIO(i915))
> pvc_whitelist_build(engine);
> @@ -2828,7 +2833,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt,
> {
> struct drm_i915_private *i915 = gt->i915;
>
> - if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))
> + if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915))
> wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
>
> /*
> @@ -2881,7 +2886,8 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> }
>
> if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
> - IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
> + IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER) ||
> + IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 74), IP_VER(12, 74)))
> /* Wa_14017856879 */
> wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 7b1c8de2f9cb..6e1b9c53a22a 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -3196,7 +3196,7 @@ u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
> struct intel_gt *gt = to_gt(i915);
>
> /* Wa_18013179988 */
> - if (IS_DG2(i915) || IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
> + if (IS_DG2(i915) || IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) {
> intel_wakeref_t wakeref;
> u32 reg, shift;
>
> --
> 2.25.1
>
next prev parent reply other threads:[~2024-01-18 23:22 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-08 12:27 [PATCH v1 0/3] Extend ARL support Haridhar Kalvala
2024-01-08 12:27 ` [PATCH v1 1/3] drm/i915: Add additional ARL PCI IDs Haridhar Kalvala
2024-01-18 23:01 ` Matt Atwood
2024-01-08 12:27 ` [PATCH v1 2/3] drm/i915/xelpg: Extend driver code of Xe_LPG to Xe_LPG+ Haridhar Kalvala
2024-01-08 14:49 ` Matt Roper
2024-01-08 12:27 ` [PATCH v1 3/3] drm/i915/xelpg: Extend some workarounds/tuning to gfx version 12.74 Haridhar Kalvala
2024-01-18 23:22 ` Matt Atwood [this message]
2024-01-08 13:33 ` ✗ Fi.CI.SPARSE: warning for Extend ARL support Patchwork
2024-01-08 13:47 ` ✓ Fi.CI.BAT: success " Patchwork
2024-01-08 15:37 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-01-18 23:33 ` Matt Roper
2024-01-19 9:44 ` Kalvala, Haridhar
-- strict thread matches above, loose matches on Subject: below --
2023-12-21 14:32 [PATCH v1 0/3] " Haridhar Kalvala
2023-12-21 14:32 ` [PATCH v1 3/3] drm/i915/xelpg: Extend some workarounds/tuning to gfx version 12.74 Haridhar Kalvala
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ZamyyoqLPEGNTHNw@msatwood-mobl \
--to=matthew.s.atwood@intel.com \
--cc=haridhar.kalvala@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=matthew.d.roper@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.