From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EF9E1429F for ; Mon, 29 Jan 2024 19:10:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706555455; cv=none; b=SAqah6O7ch47SvLNLp0AICB4SI76o4Y1EGePrjxB/fnfMuepShLEpII2r8Utxtve9LtVV7IXz3XdoCevPghMedvuozhGC4CBdBp+9lbTKp/ce1V5ZVPG/19OaqUGskv8wzSpAPDgnvaGv997OJoXCmkZXAbPMWX2LbIEKj6Kseo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706555455; c=relaxed/simple; bh=4uPdPIh+BSYrwh1ae3IlzCJs09fYGE+36cbcghzaq2w=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=p5TGOV3upMycMBUxNTUcPNHVftUfpSnEQm1bPyAl1FZdRSJfjSQjGnkfVQXJsxqIACdov6wr2Nk243thSommpnX7Wtr5SLFg84Xsmf7ftnrod3KMuy1WnLmRorU78wjsBYfnSHyceUhAEf8algeR/nZGZiaLChZYfjD8uK/ZF4g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=eiHlDs9s; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="eiHlDs9s" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-40e4afe9ea7so6975e9.1 for ; Mon, 29 Jan 2024 11:10:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1706555451; x=1707160251; darn=lists.linux.dev; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=AU6TkVc95eaOBFVMWV9z5un7MhQ7aknCzqqEszCri9k=; b=eiHlDs9spebdudw0YRqoec6GYDdtlozcCj/3OL7qKSmdppPGGLlVg2hmDoROhVz6ZQ PHmvYcVY66iC4YS+eYi0WtmIntxIjB0J0uelr4kp2GMhMh5xqHCbqAIsDgtV1yvv0E9D ZCu2pzTLkE0dvY0ZTWe/3PKDlaPK+Pc44OJLia4eQJT8YBTqOt3Pyhq5Hx+HmAQx3WYp smREaHnX6NeB/SoZAjJs0TLut8gI8YMw5DWdNN2Jje4Fj3yN0GP5ppigVUBXND6FxeoI c/nBsIO2w4zaGvy8ncCUxWYoq4+dPVuTigXTjsFyhLX8jmrC/zUNVJp5F6k89cXVTtA2 q+zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706555451; x=1707160251; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=AU6TkVc95eaOBFVMWV9z5un7MhQ7aknCzqqEszCri9k=; b=OK6mABXIMbEz4lH/U3yRDDZQvvcg1FMYeMp5K4RmF3rZy7lBpMLQo72qqAb14PU9UQ +YTpwFksRWxiTktGztBKzEd4THUrD+gyF7d81hJKy0B3qKwJkCIgIxM490Zo8KZF9QhR qzpIgUzAvtDIPf4FwmZwGLITG1/dVtsUlvhzPu4o+t+t7YNoNDS8tBgcpezZJ16Fa87h mg0kXIo6IMsnEWa7YuP584E68yXVs0DxXf3s9GktOjx5Io69o7XEnsHM4VcK90n5ON/p RdTn6efQiu8XMu3ArTIgKpUfOxeM4Z9ji2GGvNC2XSqNchrlTg+3VQ09TpRyhTYQHq0c 35zw== X-Gm-Message-State: AOJu0YwJGholZ80VW1qX5Sy2kZKPKgojA69R5l2Oriwq9ySIN8YflT3n wCm483QoGLE7oz+0SKTsfetlSTZWLsGotkjfJ5YXf4IyW5wGxQOC0rNwwQ+xeA== X-Google-Smtp-Source: AGHT+IGY0nwY27Z3YiRnoNH5L+IOds2289s9k0tIhdtMpJL6OK9PrRhAyVjpH8X+7Xfu0te8qf5I5A== X-Received: by 2002:a05:600c:4a96:b0:40e:61cf:af91 with SMTP id b22-20020a05600c4a9600b0040e61cfaf91mr11411wmp.7.1706555451279; Mon, 29 Jan 2024 11:10:51 -0800 (PST) Received: from google.com (185.83.140.34.bc.googleusercontent.com. [34.140.83.185]) by smtp.gmail.com with ESMTPSA id l29-20020a05600c1d1d00b0040ef8aa4822sm2990990wms.38.2024.01.29.11.10.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 11:10:50 -0800 (PST) Date: Mon, 29 Jan 2024 19:10:47 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: iommu@lists.linux.dev, Joerg Roedel , linux-arm-kernel@lists.infradead.org, Robin Murphy , Will Deacon , Eric Auger , Moritz Fischer , Michael Shavit , Nicolin Chen , patches@lists.linux.dev, Shameer Kolothum Subject: Re: [PATCH v3 04/19] iommu/arm-smmu-v3: Make STE programming independent of the callers Message-ID: References: <0-v3-d794f8d934da+411a-smmuv3_newapi_p1_jgg@nvidia.com> <4-v3-d794f8d934da+411a-smmuv3_newapi_p1_jgg@nvidia.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <4-v3-d794f8d934da+411a-smmuv3_newapi_p1_jgg@nvidia.com> Hi Jason, On Tue, Dec 05, 2023 at 03:14:36PM -0400, Jason Gunthorpe wrote: > As the comment in arm_smmu_write_strtab_ent() explains, this routine has > been limited to only work correctly in certain scenarios that the caller > must ensure. Generally the caller must put the STE into ABORT or BYPASS > before attempting to program it to something else. > > The next patches/series are going to start removing some of this logic > from the callers, and add more complex state combinations than currently. > > Thus, consolidate all the complexity here. Callers do not have to care > about what STE transition they are doing, this function will handle > everything optimally. > > Revise arm_smmu_write_strtab_ent() so it algorithmically computes the > required programming sequence to avoid creating an incoherent 'torn' STE > in the HW caches. The update algorithm follows the same design that the > driver already uses: it is safe to change bits that HW doesn't currently > use and then do a single 64 bit update, with sync's in between. > > The basic idea is to express in a bitmask what bits the HW is actually > using based on the V and CFG bits. Based on that mask we know what STE > changes are safe and which are disruptive. We can count how many 64 bit > QWORDS need a disruptive update and know if a step with V=0 is required. > > This gives two basic flows through the algorithm. > > If only a single 64 bit quantity needs disruptive replacement: > - Write the target value into all currently unused bits > - Write the single 64 bit quantity > - Zero the remaining different bits > > If multiple 64 bit quantities need disruptive replacement then do: > - Write V=0 to QWORD 0 > - Write the entire STE except QWORD 0 > - Write QWORD 0 > > With HW flushes at each step, that can be skipped if the STE didn't change > in that step. > > At this point it generates the same sequence of updates as the current > code, except that zeroing the VMID on entry to BYPASS/ABORT will do an > extra sync (this seems to be an existing bug). > > Going forward this will use a V=0 transition instead of cycling through > ABORT if a hitfull change is required. This seems more appropriate as ABORT > will fail DMAs without any logging, but dropping a DMA due to transient > V=0 is probably signaling a bug, so the C_BAD_STE is valuable. Would the driver do anything in that case, or would just print the log message? > Tested-by: Shameer Kolothum > Tested-by: Nicolin Chen > Reviewed-by: Nicolin Chen > Signed-off-by: Jason Gunthorpe > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 272 +++++++++++++++----- > 1 file changed, 208 insertions(+), 64 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index b120d836681c1c..0934f882b94e94 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -971,6 +971,101 @@ void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid) > arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); > } > > +/* > + * This algorithm updates any STE/CD to any value without creating a situation > + * where the HW can percieve a corrupted entry. HW is only required to have a 64 > + * bit atomicity with stores from the CPU, while entries are many 64 bit values > + * big. > + * > + * The algorithm works by evolving the entry toward the target in a series of > + * steps. Each step synchronizes with the HW so that the HW can not see an entry > + * torn across two steps. Upon each call cur/cur_used reflect the current > + * synchronized value seen by the HW. > + * > + * During each step the HW can observe a torn entry that has any combination of > + * the step's old/new 64 bit words. The algorithm objective is for the HW > + * behavior to always be one of current behavior, V=0, or new behavior, during > + * each step, and across all steps. > + * > + * At each step one of three actions is chosen to evolve cur to target: > + * - Update all unused bits with their target values. > + * This relies on the IGNORED behavior described in the specification > + * - Update a single 64-bit value > + * - Update all unused bits and set V=0 > + * > + * The last two actions will cause cur_used to change, which will then allow the > + * first action on the next step. > + * > + * In the most general case we can make any update in three steps: > + * - Disrupting the entry (V=0) > + * - Fill now unused bits, all bits except V > + * - Make valid (V=1), single 64 bit store > + * > + * However this disrupts the HW while it is happening. There are several > + * interesting cases where a STE/CD can be updated without disturbing the HW > + * because only a small number of bits are changing (S1DSS, CONFIG, etc) or > + * because the used bits don't intersect. We can detect this by calculating how > + * many 64 bit values need update after adjusting the unused bits and skip the > + * V=0 process. > + */ > +static bool arm_smmu_write_entry_step(__le64 *cur, const __le64 *cur_used, > + const __le64 *target, > + const __le64 *target_used, __le64 *step, > + __le64 v_bit, I think this is confusing here, I believe we have this as an argument as this function would be used for CD later, however for this series it is unnecessary, IMHO, this should be removed and added in another patch for the CD rework. > + unsigned int len) > +{ > + u8 step_used_diff = 0; > + u8 step_change = 0; > + unsigned int i; > + > + /* > + * Compute a step that has all the bits currently unused by HW set to > + * their target values. > + */ > + for (i = 0; i != len; i++) { > + step[i] = (cur[i] & cur_used[i]) | (target[i] & ~cur_used[i]); > + if (cur[i] != step[i]) > + step_change |= 1 << i; > + /* > + * Each bit indicates if the step is incorrect compared to the > + * target, considering only the used bits in the target > + */ > + if ((step[i] & target_used[i]) != (target[i] & target_used[i])) > + step_used_diff |= 1 << i; > + } > + > + if (hweight8(step_used_diff) > 1) { > + /* > + * More than 1 qword is mismatched, this cannot be done without > + * a break. Clear the V bit and go again. > + */ > + step[0] &= ~v_bit; > + } else if (!step_change && step_used_diff) { > + /* > + * Have exactly one critical qword, all the other qwords are set > + * correctly, so we can set this qword now. > + */ > + i = ffs(step_used_diff) - 1; > + step[i] = target[i]; > + } else if (!step_change) { > + /* cur == target, so all done */ > + if (memcmp(cur, target, len * sizeof(*cur)) == 0) > + return true; > + > + /* > + * All the used HW bits match, but unused bits are different. > + * Set them as well. Technically this isn't necessary but it > + * brings the entry to the full target state, so if there are > + * bugs in the mask calculation this will obscure them. > + */ > + memcpy(step, target, len * sizeof(*step)); > + } > + > + for (i = 0; i != len; i++) > + WRITE_ONCE(cur[i], step[i]); > + return false; > +} > + > static void arm_smmu_sync_cd(struct arm_smmu_master *master, > int ssid, bool leaf) > { > @@ -1248,37 +1343,115 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) > arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); > } > > +/* > + * Based on the value of ent report which bits of the STE the HW will access. It > + * would be nice if this was complete according to the spec, but minimally it > + * has to capture the bits this driver uses. > + */ > +static void arm_smmu_get_ste_used(const struct arm_smmu_ste *ent, > + struct arm_smmu_ste *used_bits) > +{ > + memset(used_bits, 0, sizeof(*used_bits)); > + > + used_bits->data[0] = cpu_to_le64(STRTAB_STE_0_V); > + if (!(ent->data[0] & cpu_to_le64(STRTAB_STE_0_V))) > + return; > + > + /* > + * If S1 is enabled S1DSS is valid, see 13.5 Summary of > + * attribute/permission configuration fields for the SHCFG behavior. > + */ > + if (FIELD_GET(STRTAB_STE_0_CFG, le64_to_cpu(ent->data[0])) & 1 && > + FIELD_GET(STRTAB_STE_1_S1DSS, le64_to_cpu(ent->data[1])) == > + STRTAB_STE_1_S1DSS_BYPASS) > + used_bits->data[1] |= cpu_to_le64(STRTAB_STE_1_SHCFG); > + > + used_bits->data[0] |= cpu_to_le64(STRTAB_STE_0_CFG); > + switch (FIELD_GET(STRTAB_STE_0_CFG, le64_to_cpu(ent->data[0]))) { > + case STRTAB_STE_0_CFG_ABORT: > + break; > + case STRTAB_STE_0_CFG_BYPASS: > + used_bits->data[1] |= cpu_to_le64(STRTAB_STE_1_SHCFG); > + break; > + case STRTAB_STE_0_CFG_S1_TRANS: > + used_bits->data[0] |= cpu_to_le64(STRTAB_STE_0_S1FMT | > + STRTAB_STE_0_S1CTXPTR_MASK | > + STRTAB_STE_0_S1CDMAX); > + used_bits->data[1] |= > + cpu_to_le64(STRTAB_STE_1_S1DSS | STRTAB_STE_1_S1CIR | > + STRTAB_STE_1_S1COR | STRTAB_STE_1_S1CSH | > + STRTAB_STE_1_S1STALLD | STRTAB_STE_1_STRW); > + used_bits->data[1] |= cpu_to_le64(STRTAB_STE_1_EATS); > + break; AFAIU, this is missing something like (while passing smmu->features) used_bits->data[2] |= features & ARM_SMMU_FEAT_NESTING ? cpu_to_le64(STRTAB_STE_2_S2VMID) : 0; As the SMMUv3 manual says: “ For a Non-secure STE when stage 2 is implemented (SMMU_IDR0.S2P == 1) translations resulting from a StreamWorld == NS-EL1 configuration are VMID-tagged with S2VMID when either of stage 1 (Config[0] == 1) or stage 2 (Config[1] == 1) provide translation.“ Which means in case of S1=>S2 switch or vice versa this algorithm will ignore VMID while it is used. > + case STRTAB_STE_0_CFG_S2_TRANS: > + used_bits->data[1] |= > + cpu_to_le64(STRTAB_STE_1_EATS | STRTAB_STE_1_SHCFG); > + used_bits->data[2] |= > + cpu_to_le64(STRTAB_STE_2_S2VMID | STRTAB_STE_2_VTCR | > + STRTAB_STE_2_S2AA64 | STRTAB_STE_2_S2ENDI | > + STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2R); > + used_bits->data[3] |= cpu_to_le64(STRTAB_STE_3_S2TTB_MASK); > + break; > + > + default: > + memset(used_bits, 0xFF, sizeof(*used_bits)); > + WARN_ON(true); > + } > +} > + > +static bool arm_smmu_write_ste_step(struct arm_smmu_ste *cur, > + const struct arm_smmu_ste *target, > + const struct arm_smmu_ste *target_used) > +{ > + struct arm_smmu_ste cur_used; > + struct arm_smmu_ste step; > + > + arm_smmu_get_ste_used(cur, &cur_used); > + return arm_smmu_write_entry_step(cur->data, cur_used.data, target->data, > + target_used->data, step.data, > + cpu_to_le64(STRTAB_STE_0_V), > + ARRAY_SIZE(cur->data)); > +} > + > +static void arm_smmu_write_ste(struct arm_smmu_device *smmu, u32 sid, > + struct arm_smmu_ste *ste, > + const struct arm_smmu_ste *target) > +{ > + struct arm_smmu_ste target_used; > + int i; > + > + arm_smmu_get_ste_used(target, &target_used); > + /* Masks in arm_smmu_get_ste_used() are up to date */ > + for (i = 0; i != ARRAY_SIZE(target->data); i++) > + WARN_ON_ONCE(target->data[i] & ~target_used.data[i]); In what situation this would be triggered, is that for future proofing, maybe we can move it to arm_smmu_get_ste_used()? > + > + while (true) { > + if (arm_smmu_write_ste_step(ste, target, &target_used)) > + break; > + arm_smmu_sync_ste_for_sid(smmu, sid); > + } > + > + /* It's likely that we'll want to use the new STE soon */ > + if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH)) { > + struct arm_smmu_cmdq_ent > + prefetch_cmd = { .opcode = CMDQ_OP_PREFETCH_CFG, > + .prefetch = { > + .sid = sid, > + } }; > + > + arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd); > + } > +} > + > static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, > struct arm_smmu_ste *dst) > { > - /* > - * This is hideously complicated, but we only really care about > - * three cases at the moment: > - * > - * 1. Invalid (all zero) -> bypass/fault (init) > - * 2. Bypass/fault -> translation/bypass (attach) > - * 3. Translation/bypass -> bypass/fault (detach) > - * > - * Given that we can't update the STE atomically and the SMMU > - * doesn't read the thing in a defined order, that leaves us > - * with the following maintenance requirements: > - * > - * 1. Update Config, return (init time STEs aren't live) > - * 2. Write everything apart from dword 0, sync, write dword 0, sync > - * 3. Update Config, sync > - */ > - u64 val = le64_to_cpu(dst->data[0]); > - bool ste_live = false; > + u64 val; > struct arm_smmu_device *smmu = master->smmu; > struct arm_smmu_ctx_desc_cfg *cd_table = NULL; > struct arm_smmu_s2_cfg *s2_cfg = NULL; > struct arm_smmu_domain *smmu_domain = master->domain; > - struct arm_smmu_cmdq_ent prefetch_cmd = { > - .opcode = CMDQ_OP_PREFETCH_CFG, > - .prefetch = { > - .sid = sid, > - }, > - }; > + struct arm_smmu_ste target = {}; > > if (smmu_domain) { > switch (smmu_domain->stage) { > @@ -1293,22 +1466,6 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, > } > } > > - if (val & STRTAB_STE_0_V) { > - switch (FIELD_GET(STRTAB_STE_0_CFG, val)) { > - case STRTAB_STE_0_CFG_BYPASS: > - break; > - case STRTAB_STE_0_CFG_S1_TRANS: > - case STRTAB_STE_0_CFG_S2_TRANS: > - ste_live = true; > - break; > - case STRTAB_STE_0_CFG_ABORT: > - BUG_ON(!disable_bypass); > - break; > - default: > - BUG(); /* STE corruption */ > - } > - } > - > /* Nuke the existing STE_0 value, as we're going to rewrite it */ > val = STRTAB_STE_0_V; > > @@ -1319,16 +1476,11 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, > else > val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS); > > - dst->data[0] = cpu_to_le64(val); > - dst->data[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG, > + target.data[0] = cpu_to_le64(val); > + target.data[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG, > STRTAB_STE_1_SHCFG_INCOMING)); > - dst->data[2] = 0; /* Nuke the VMID */ > - /* > - * The SMMU can perform negative caching, so we must sync > - * the STE regardless of whether the old value was live. > - */ > - if (smmu) > - arm_smmu_sync_ste_for_sid(smmu, sid); > + target.data[2] = 0; /* Nuke the VMID */ > + arm_smmu_write_ste(smmu, sid, dst, &target); > return; > } > > @@ -1336,8 +1488,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, > u64 strw = smmu->features & ARM_SMMU_FEAT_E2H ? > STRTAB_STE_1_STRW_EL2 : STRTAB_STE_1_STRW_NSEL1; > > - BUG_ON(ste_live); > - dst->data[1] = cpu_to_le64( > + target.data[1] = cpu_to_le64( > FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) | > FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) | > FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) | > @@ -1346,7 +1497,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, > > if (smmu->features & ARM_SMMU_FEAT_STALLS && > !master->stall_enabled) > - dst->data[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD); > + target.data[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD); > > val |= (cd_table->cdtab_dma & STRTAB_STE_0_S1CTXPTR_MASK) | > FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) | > @@ -1355,8 +1506,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, > } > > if (s2_cfg) { > - BUG_ON(ste_live); > - dst->data[2] = cpu_to_le64( > + target.data[2] = cpu_to_le64( > FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | > FIELD_PREP(STRTAB_STE_2_VTCR, s2_cfg->vtcr) | > #ifdef __BIG_ENDIAN > @@ -1365,23 +1515,17 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, > STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 | > STRTAB_STE_2_S2R); > > - dst->data[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); > + target.data[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); > > val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS); > } > > if (master->ats_enabled) > - dst->data[1] |= cpu_to_le64(FIELD_PREP(STRTAB_STE_1_EATS, > + target.data[1] |= cpu_to_le64(FIELD_PREP(STRTAB_STE_1_EATS, > STRTAB_STE_1_EATS_TRANS)); > > - arm_smmu_sync_ste_for_sid(smmu, sid); > - /* See comment in arm_smmu_write_ctx_desc() */ > - WRITE_ONCE(dst->data[0], cpu_to_le64(val)); > - arm_smmu_sync_ste_for_sid(smmu, sid); > - > - /* It's likely that we'll want to use the new STE soon */ > - if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH)) > - arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd); > + target.data[0] = cpu_to_le64(val); > + arm_smmu_write_ste(smmu, sid, dst, &target); > } > > static void arm_smmu_init_bypass_stes(struct arm_smmu_ste *strtab, > -- > 2.43.0 > Thanks, Mostafa From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8A85C47DDB for ; Mon, 29 Jan 2024 19:11:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gxezL72DyFynO1u+JtkNp26DB85qmV76ZtbaJUGtE2s=; b=OtO0PG67BGGdtt arCePQkYibTv+NN5MvVSWvEmw4iLNszZoAan8rNCIXH8oy+rP92vrt5+PLNVkU/oUDAZRB+6mNBHy HFYSOLOa5lDdTk8G8eSKfEX+MqaEs0m44VB2qjGlNTxE5gt3T1WDU8/ow1n/BWzCuUEGtVihR0yYm /5b0JGoLslw6P7AAlsGOO9l+4kwlhhIn5eB1TtS2JsBM1ABhMnB8tma2LvDs2lSlVge1HShv2NKD2 mUsWuAi3629GuIas8wF3yy7b+eBk1Jp6tqbaa+CebjckpsBgheqzJzHBgfzrVx5f4bmDRRRrXMLWN +sVdMqeuziQ0X6QCDsrA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rUX20-0000000E4DW-2Ohy; Mon, 29 Jan 2024 19:10:56 +0000 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rUX1y-0000000E4D7-0bCx for linux-arm-kernel@lists.infradead.org; Mon, 29 Jan 2024 19:10:55 +0000 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-40e4afe9ea7so6955e9.1 for ; Mon, 29 Jan 2024 11:10:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1706555451; x=1707160251; darn=lists.infradead.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=AU6TkVc95eaOBFVMWV9z5un7MhQ7aknCzqqEszCri9k=; b=Qoqf4Toa3y0D7RRmlPTo3GsgoOo2pVzAnO+BqPri+FwWZlJBHJSyoYJLmu1AI3rpah wQSVItuckA6nIUzsbuI4mI5uwQreT8F3ktVkZ/eABimQMpPL1psVEUiIKCHMVpCdji97 YJts2uFAOgUKX51P1+EcqB2SodXOMmVBNjoWbD88rfp2NTMgOyeN4+aEnBly42DG7ERL YI6eNdCHHKZw1fsI4WL9byPAF/sbjfbYo5sb7xOHf7sK4XkcSIRfWVsZn/EkWUDh/3vj Gc+54aLnmT4k3uttkgXsfTr2q88Styh2u5TKyoIJou31UCwl/hJInFAJi1JBFdK3dzw4 207g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706555451; x=1707160251; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=AU6TkVc95eaOBFVMWV9z5un7MhQ7aknCzqqEszCri9k=; b=n5+DBapRdPVgkAfDmRkwhft01sm2DW9mmuF60Ave78nR/ls81ijnXGOF4kvoKTbUek UO18wIg3y5XeYwvKt1aUMbvI20AskiRUBNBVmOLOpHRfFfk63jnK6FdfJZXsmosKj0x6 HoH2G/2rnmgDTn3bx1JO8LAWA20jXnBc7EEfdv6rSsXYU3T8rmiG/V3S3/O1rpfVkVYv QXCSxcRC+AxSeXroyGJ9Lq4F6iIb4xR7W76Zpc0PagNQDuJHBixJ4S+2nYXxp8HjmXLg e9icqb6CTVCCt8KymbH2ik3d3gWGIBfLIWFumkLVhOJr/oKLvr70MDg5F4Ki3xHvCqW0 zuXA== X-Gm-Message-State: AOJu0YzEtIypdB143iKhaZ6I6y1LF7VIWAZujL6F8b1PzNS7FeMTeuCx z5IvTP7MdgMISsNHrbU3fix6opT22kif1Ptkw/uJDACay+JJxiKZP2drHu7FLg== X-Google-Smtp-Source: AGHT+IGY0nwY27Z3YiRnoNH5L+IOds2289s9k0tIhdtMpJL6OK9PrRhAyVjpH8X+7Xfu0te8qf5I5A== X-Received: by 2002:a05:600c:4a96:b0:40e:61cf:af91 with SMTP id b22-20020a05600c4a9600b0040e61cfaf91mr11411wmp.7.1706555451279; Mon, 29 Jan 2024 11:10:51 -0800 (PST) Received: from google.com (185.83.140.34.bc.googleusercontent.com. [34.140.83.185]) by smtp.gmail.com with ESMTPSA id l29-20020a05600c1d1d00b0040ef8aa4822sm2990990wms.38.2024.01.29.11.10.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 11:10:50 -0800 (PST) Date: Mon, 29 Jan 2024 19:10:47 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: iommu@lists.linux.dev, Joerg Roedel , linux-arm-kernel@lists.infradead.org, Robin Murphy , Will Deacon , Eric Auger , Moritz Fischer , Michael Shavit , Nicolin Chen , patches@lists.linux.dev, Shameer Kolothum Subject: Re: [PATCH v3 04/19] iommu/arm-smmu-v3: Make STE programming independent of the callers Message-ID: References: <0-v3-d794f8d934da+411a-smmuv3_newapi_p1_jgg@nvidia.com> <4-v3-d794f8d934da+411a-smmuv3_newapi_p1_jgg@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <4-v3-d794f8d934da+411a-smmuv3_newapi_p1_jgg@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240129_111054_241452_DB1D5D72 X-CRM114-Status: GOOD ( 66.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SGkgSmFzb24sCgpPbiBUdWUsIERlYyAwNSwgMjAyMyBhdCAwMzoxNDozNlBNIC0wNDAwLCBKYXNv biBHdW50aG9ycGUgd3JvdGU6Cj4gQXMgdGhlIGNvbW1lbnQgaW4gYXJtX3NtbXVfd3JpdGVfc3Ry dGFiX2VudCgpIGV4cGxhaW5zLCB0aGlzIHJvdXRpbmUgaGFzCj4gYmVlbiBsaW1pdGVkIHRvIG9u bHkgd29yayBjb3JyZWN0bHkgaW4gY2VydGFpbiBzY2VuYXJpb3MgdGhhdCB0aGUgY2FsbGVyCj4g bXVzdCBlbnN1cmUuIEdlbmVyYWxseSB0aGUgY2FsbGVyIG11c3QgcHV0IHRoZSBTVEUgaW50byBB Qk9SVCBvciBCWVBBU1MKPiBiZWZvcmUgYXR0ZW1wdGluZyB0byBwcm9ncmFtIGl0IHRvIHNvbWV0 aGluZyBlbHNlLgo+IAo+IFRoZSBuZXh0IHBhdGNoZXMvc2VyaWVzIGFyZSBnb2luZyB0byBzdGFy dCByZW1vdmluZyBzb21lIG9mIHRoaXMgbG9naWMKPiBmcm9tIHRoZSBjYWxsZXJzLCBhbmQgYWRk IG1vcmUgY29tcGxleCBzdGF0ZSBjb21iaW5hdGlvbnMgdGhhbiBjdXJyZW50bHkuCj4gCj4gVGh1 cywgY29uc29saWRhdGUgYWxsIHRoZSBjb21wbGV4aXR5IGhlcmUuIENhbGxlcnMgZG8gbm90IGhh dmUgdG8gY2FyZQo+IGFib3V0IHdoYXQgU1RFIHRyYW5zaXRpb24gdGhleSBhcmUgZG9pbmcsIHRo aXMgZnVuY3Rpb24gd2lsbCBoYW5kbGUKPiBldmVyeXRoaW5nIG9wdGltYWxseS4KPiAKPiBSZXZp c2UgYXJtX3NtbXVfd3JpdGVfc3RydGFiX2VudCgpIHNvIGl0IGFsZ29yaXRobWljYWxseSBjb21w dXRlcyB0aGUKPiByZXF1aXJlZCBwcm9ncmFtbWluZyBzZXF1ZW5jZSB0byBhdm9pZCBjcmVhdGlu ZyBhbiBpbmNvaGVyZW50ICd0b3JuJyBTVEUKPiBpbiB0aGUgSFcgY2FjaGVzLiBUaGUgdXBkYXRl IGFsZ29yaXRobSBmb2xsb3dzIHRoZSBzYW1lIGRlc2lnbiB0aGF0IHRoZQo+IGRyaXZlciBhbHJl YWR5IHVzZXM6IGl0IGlzIHNhZmUgdG8gY2hhbmdlIGJpdHMgdGhhdCBIVyBkb2Vzbid0IGN1cnJl bnRseQo+IHVzZSBhbmQgdGhlbiBkbyBhIHNpbmdsZSA2NCBiaXQgdXBkYXRlLCB3aXRoIHN5bmMn cyBpbiBiZXR3ZWVuLgo+IAo+IFRoZSBiYXNpYyBpZGVhIGlzIHRvIGV4cHJlc3MgaW4gYSBiaXRt YXNrIHdoYXQgYml0cyB0aGUgSFcgaXMgYWN0dWFsbHkKPiB1c2luZyBiYXNlZCBvbiB0aGUgViBh bmQgQ0ZHIGJpdHMuIEJhc2VkIG9uIHRoYXQgbWFzayB3ZSBrbm93IHdoYXQgU1RFCj4gY2hhbmdl cyBhcmUgc2FmZSBhbmQgd2hpY2ggYXJlIGRpc3J1cHRpdmUuIFdlIGNhbiBjb3VudCBob3cgbWFu eSA2NCBiaXQKPiBRV09SRFMgbmVlZCBhIGRpc3J1cHRpdmUgdXBkYXRlIGFuZCBrbm93IGlmIGEg c3RlcCB3aXRoIFY9MCBpcyByZXF1aXJlZC4KPiAKPiBUaGlzIGdpdmVzIHR3byBiYXNpYyBmbG93 cyB0aHJvdWdoIHRoZSBhbGdvcml0aG0uCj4gCj4gSWYgb25seSBhIHNpbmdsZSA2NCBiaXQgcXVh bnRpdHkgbmVlZHMgZGlzcnVwdGl2ZSByZXBsYWNlbWVudDoKPiAgLSBXcml0ZSB0aGUgdGFyZ2V0 IHZhbHVlIGludG8gYWxsIGN1cnJlbnRseSB1bnVzZWQgYml0cwo+ICAtIFdyaXRlIHRoZSBzaW5n bGUgNjQgYml0IHF1YW50aXR5Cj4gIC0gWmVybyB0aGUgcmVtYWluaW5nIGRpZmZlcmVudCBiaXRz Cj4gCj4gSWYgbXVsdGlwbGUgNjQgYml0IHF1YW50aXRpZXMgbmVlZCBkaXNydXB0aXZlIHJlcGxh Y2VtZW50IHRoZW4gZG86Cj4gIC0gV3JpdGUgVj0wIHRvIFFXT1JEIDAKPiAgLSBXcml0ZSB0aGUg ZW50aXJlIFNURSBleGNlcHQgUVdPUkQgMAo+ICAtIFdyaXRlIFFXT1JEIDAKPiAKPiBXaXRoIEhX IGZsdXNoZXMgYXQgZWFjaCBzdGVwLCB0aGF0IGNhbiBiZSBza2lwcGVkIGlmIHRoZSBTVEUgZGlk bid0IGNoYW5nZQo+IGluIHRoYXQgc3RlcC4KPiAKPiBBdCB0aGlzIHBvaW50IGl0IGdlbmVyYXRl cyB0aGUgc2FtZSBzZXF1ZW5jZSBvZiB1cGRhdGVzIGFzIHRoZSBjdXJyZW50Cj4gY29kZSwgZXhj ZXB0IHRoYXQgemVyb2luZyB0aGUgVk1JRCBvbiBlbnRyeSB0byBCWVBBU1MvQUJPUlQgd2lsbCBk byBhbgo+IGV4dHJhIHN5bmMgKHRoaXMgc2VlbXMgdG8gYmUgYW4gZXhpc3RpbmcgYnVnKS4KPiAK PiBHb2luZyBmb3J3YXJkIHRoaXMgd2lsbCB1c2UgYSBWPTAgdHJhbnNpdGlvbiBpbnN0ZWFkIG9m IGN5Y2xpbmcgdGhyb3VnaAo+IEFCT1JUIGlmIGEgaGl0ZnVsbCBjaGFuZ2UgaXMgcmVxdWlyZWQu IFRoaXMgc2VlbXMgbW9yZSBhcHByb3ByaWF0ZSBhcyBBQk9SVAo+IHdpbGwgZmFpbCBETUFzIHdp dGhvdXQgYW55IGxvZ2dpbmcsIGJ1dCBkcm9wcGluZyBhIERNQSBkdWUgdG8gdHJhbnNpZW50Cj4g Vj0wIGlzIHByb2JhYmx5IHNpZ25hbGluZyBhIGJ1Zywgc28gdGhlIENfQkFEX1NURSBpcyB2YWx1 YWJsZS4KV291bGQgdGhlIGRyaXZlciBkbyBhbnl0aGluZyBpbiB0aGF0IGNhc2UsIG9yIHdvdWxk IGp1c3QgcHJpbnQgdGhlIGxvZyBtZXNzYWdlPwoKPiBUZXN0ZWQtYnk6IFNoYW1lZXIgS29sb3Ro dW0gPHNoYW1lZXJhbGkua29sb3RodW0udGhvZGlAaHVhd2VpLmNvbT4KPiBUZXN0ZWQtYnk6IE5p Y29saW4gQ2hlbiA8bmljb2xpbmNAbnZpZGlhLmNvbT4KPiBSZXZpZXdlZC1ieTogTmljb2xpbiBD aGVuIDxuaWNvbGluY0BudmlkaWEuY29tPgo+IFNpZ25lZC1vZmYtYnk6IEphc29uIEd1bnRob3Jw ZSA8amdnQG52aWRpYS5jb20+Cj4gLS0tCj4gIGRyaXZlcnMvaW9tbXUvYXJtL2FybS1zbW11LXYz L2FybS1zbW11LXYzLmMgfCAyNzIgKysrKysrKysrKysrKysrLS0tLS0KPiAgMSBmaWxlIGNoYW5n ZWQsIDIwOCBpbnNlcnRpb25zKCspLCA2NCBkZWxldGlvbnMoLSkKPiAKPiBkaWZmIC0tZ2l0IGEv ZHJpdmVycy9pb21tdS9hcm0vYXJtLXNtbXUtdjMvYXJtLXNtbXUtdjMuYyBiL2RyaXZlcnMvaW9t bXUvYXJtL2FybS1zbW11LXYzL2FybS1zbW11LXYzLmMKPiBpbmRleCBiMTIwZDgzNjY4MWMxYy4u MDkzNGY4ODJiOTRlOTQgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9pb21tdS9hcm0vYXJtLXNtbXUt djMvYXJtLXNtbXUtdjMuYwo+ICsrKyBiL2RyaXZlcnMvaW9tbXUvYXJtL2FybS1zbW11LXYzL2Fy bS1zbW11LXYzLmMKPiBAQCAtOTcxLDYgKzk3MSwxMDEgQEAgdm9pZCBhcm1fc21tdV90bGJfaW52 X2FzaWQoc3RydWN0IGFybV9zbW11X2RldmljZSAqc21tdSwgdTE2IGFzaWQpCj4gIAlhcm1fc21t dV9jbWRxX2lzc3VlX2NtZF93aXRoX3N5bmMoc21tdSwgJmNtZCk7Cj4gIH0KPiAgCj4gKy8qCj4g KyAqIFRoaXMgYWxnb3JpdGhtIHVwZGF0ZXMgYW55IFNURS9DRCB0byBhbnkgdmFsdWUgd2l0aG91 dCBjcmVhdGluZyBhIHNpdHVhdGlvbgo+ICsgKiB3aGVyZSB0aGUgSFcgY2FuIHBlcmNpZXZlIGEg Y29ycnVwdGVkIGVudHJ5LiBIVyBpcyBvbmx5IHJlcXVpcmVkIHRvIGhhdmUgYSA2NAo+ICsgKiBi aXQgYXRvbWljaXR5IHdpdGggc3RvcmVzIGZyb20gdGhlIENQVSwgd2hpbGUgZW50cmllcyBhcmUg bWFueSA2NCBiaXQgdmFsdWVzCj4gKyAqIGJpZy4KPiArICoKPiArICogVGhlIGFsZ29yaXRobSB3 b3JrcyBieSBldm9sdmluZyB0aGUgZW50cnkgdG93YXJkIHRoZSB0YXJnZXQgaW4gYSBzZXJpZXMg b2YKPiArICogc3RlcHMuIEVhY2ggc3RlcCBzeW5jaHJvbml6ZXMgd2l0aCB0aGUgSFcgc28gdGhh dCB0aGUgSFcgY2FuIG5vdCBzZWUgYW4gZW50cnkKPiArICogdG9ybiBhY3Jvc3MgdHdvIHN0ZXBz LiBVcG9uIGVhY2ggY2FsbCBjdXIvY3VyX3VzZWQgcmVmbGVjdCB0aGUgY3VycmVudAo+ICsgKiBz eW5jaHJvbml6ZWQgdmFsdWUgc2VlbiBieSB0aGUgSFcuCj4gKyAqCj4gKyAqIER1cmluZyBlYWNo IHN0ZXAgdGhlIEhXIGNhbiBvYnNlcnZlIGEgdG9ybiBlbnRyeSB0aGF0IGhhcyBhbnkgY29tYmlu YXRpb24gb2YKPiArICogdGhlIHN0ZXAncyBvbGQvbmV3IDY0IGJpdCB3b3Jkcy4gVGhlIGFsZ29y aXRobSBvYmplY3RpdmUgaXMgZm9yIHRoZSBIVwo+ICsgKiBiZWhhdmlvciB0byBhbHdheXMgYmUg b25lIG9mIGN1cnJlbnQgYmVoYXZpb3IsIFY9MCwgb3IgbmV3IGJlaGF2aW9yLCBkdXJpbmcKPiAr ICogZWFjaCBzdGVwLCBhbmQgYWNyb3NzIGFsbCBzdGVwcy4KPiArICoKPiArICogQXQgZWFjaCBz dGVwIG9uZSBvZiB0aHJlZSBhY3Rpb25zIGlzIGNob3NlbiB0byBldm9sdmUgY3VyIHRvIHRhcmdl dDoKPiArICogIC0gVXBkYXRlIGFsbCB1bnVzZWQgYml0cyB3aXRoIHRoZWlyIHRhcmdldCB2YWx1 ZXMuCj4gKyAqICAgIFRoaXMgcmVsaWVzIG9uIHRoZSBJR05PUkVEIGJlaGF2aW9yIGRlc2NyaWJl ZCBpbiB0aGUgc3BlY2lmaWNhdGlvbgo+ICsgKiAgLSBVcGRhdGUgYSBzaW5nbGUgNjQtYml0IHZh bHVlCj4gKyAqICAtIFVwZGF0ZSBhbGwgdW51c2VkIGJpdHMgYW5kIHNldCBWPTAKPiArICoKPiAr ICogVGhlIGxhc3QgdHdvIGFjdGlvbnMgd2lsbCBjYXVzZSBjdXJfdXNlZCB0byBjaGFuZ2UsIHdo aWNoIHdpbGwgdGhlbiBhbGxvdyB0aGUKPiArICogZmlyc3QgYWN0aW9uIG9uIHRoZSBuZXh0IHN0 ZXAuCj4gKyAqCj4gKyAqIEluIHRoZSBtb3N0IGdlbmVyYWwgY2FzZSB3ZSBjYW4gbWFrZSBhbnkg dXBkYXRlIGluIHRocmVlIHN0ZXBzOgo+ICsgKiAgLSBEaXNydXB0aW5nIHRoZSBlbnRyeSAoVj0w KQo+ICsgKiAgLSBGaWxsIG5vdyB1bnVzZWQgYml0cywgYWxsIGJpdHMgZXhjZXB0IFYKPiArICog IC0gTWFrZSB2YWxpZCAoVj0xKSwgc2luZ2xlIDY0IGJpdCBzdG9yZQo+ICsgKgo+ICsgKiBIb3dl dmVyIHRoaXMgZGlzcnVwdHMgdGhlIEhXIHdoaWxlIGl0IGlzIGhhcHBlbmluZy4gVGhlcmUgYXJl IHNldmVyYWwKPiArICogaW50ZXJlc3RpbmcgY2FzZXMgd2hlcmUgYSBTVEUvQ0QgY2FuIGJlIHVw ZGF0ZWQgd2l0aG91dCBkaXN0dXJiaW5nIHRoZSBIVwo+ICsgKiBiZWNhdXNlIG9ubHkgYSBzbWFs bCBudW1iZXIgb2YgYml0cyBhcmUgY2hhbmdpbmcgKFMxRFNTLCBDT05GSUcsIGV0Yykgb3IKPiAr ICogYmVjYXVzZSB0aGUgdXNlZCBiaXRzIGRvbid0IGludGVyc2VjdC4gV2UgY2FuIGRldGVjdCB0 aGlzIGJ5IGNhbGN1bGF0aW5nIGhvdwo+ICsgKiBtYW55IDY0IGJpdCB2YWx1ZXMgbmVlZCB1cGRh dGUgYWZ0ZXIgYWRqdXN0aW5nIHRoZSB1bnVzZWQgYml0cyBhbmQgc2tpcCB0aGUKPiArICogVj0w IHByb2Nlc3MuCj4gKyAqLwo+ICtzdGF0aWMgYm9vbCBhcm1fc21tdV93cml0ZV9lbnRyeV9zdGVw KF9fbGU2NCAqY3VyLCBjb25zdCBfX2xlNjQgKmN1cl91c2VkLAo+ICsJCQkJICAgICAgY29uc3Qg X19sZTY0ICp0YXJnZXQsCj4gKwkJCQkgICAgICBjb25zdCBfX2xlNjQgKnRhcmdldF91c2VkLCBf X2xlNjQgKnN0ZXAsCj4gKwkJCQkgICAgICBfX2xlNjQgdl9iaXQsCkkgdGhpbmsgdGhpcyBpcyBj b25mdXNpbmcgaGVyZSwgSSBiZWxpZXZlIHdlIGhhdmUgdGhpcyBhcyBhbiBhcmd1bWVudCBhcyB0 aGlzCmZ1bmN0aW9uIHdvdWxkIGJlIHVzZWQgZm9yIENEIGxhdGVyLCBob3dldmVyIGZvciB0aGlz IHNlcmllcyBpdCBpcyB1bm5lY2Vzc2FyeSwKSU1ITywgdGhpcyBzaG91bGQgYmUgcmVtb3ZlZCBh bmQgYWRkZWQgaW4gYW5vdGhlciBwYXRjaCBmb3IgdGhlIENEIHJld29yay4KCj4gKwkJCQkgICAg ICB1bnNpZ25lZCBpbnQgbGVuKQo+ICt7Cj4gKwl1OCBzdGVwX3VzZWRfZGlmZiA9IDA7Cj4gKwl1 OCBzdGVwX2NoYW5nZSA9IDA7Cj4gKwl1bnNpZ25lZCBpbnQgaTsKPiArCj4gKwkvKgo+ICsJICog Q29tcHV0ZSBhIHN0ZXAgdGhhdCBoYXMgYWxsIHRoZSBiaXRzIGN1cnJlbnRseSB1bnVzZWQgYnkg SFcgc2V0IHRvCj4gKwkgKiB0aGVpciB0YXJnZXQgdmFsdWVzLgo+ICsJICovCj4gKwlmb3IgKGkg PSAwOyBpICE9IGxlbjsgaSsrKSB7Cj4gKwkJc3RlcFtpXSA9IChjdXJbaV0gJiBjdXJfdXNlZFtp XSkgfCAodGFyZ2V0W2ldICYgfmN1cl91c2VkW2ldKTsKPiArCQlpZiAoY3VyW2ldICE9IHN0ZXBb aV0pCj4gKwkJCXN0ZXBfY2hhbmdlIHw9IDEgPDwgaTsKPiArCQkvKgo+ICsJCSAqIEVhY2ggYml0 IGluZGljYXRlcyBpZiB0aGUgc3RlcCBpcyBpbmNvcnJlY3QgY29tcGFyZWQgdG8gdGhlCj4gKwkJ ICogdGFyZ2V0LCBjb25zaWRlcmluZyBvbmx5IHRoZSB1c2VkIGJpdHMgaW4gdGhlIHRhcmdldAo+ ICsJCSAqLwo+ICsJCWlmICgoc3RlcFtpXSAmIHRhcmdldF91c2VkW2ldKSAhPSAodGFyZ2V0W2ld ICYgdGFyZ2V0X3VzZWRbaV0pKQo+ICsJCQlzdGVwX3VzZWRfZGlmZiB8PSAxIDw8IGk7Cj4gKwl9 Cj4gKwo+ICsJaWYgKGh3ZWlnaHQ4KHN0ZXBfdXNlZF9kaWZmKSA+IDEpIHsKPiArCQkvKgo+ICsJ CSAqIE1vcmUgdGhhbiAxIHF3b3JkIGlzIG1pc21hdGNoZWQsIHRoaXMgY2Fubm90IGJlIGRvbmUg d2l0aG91dAo+ICsJCSAqIGEgYnJlYWsuIENsZWFyIHRoZSBWIGJpdCBhbmQgZ28gYWdhaW4uCj4g KwkJICovCj4gKwkJc3RlcFswXSAmPSB+dl9iaXQ7Cj4gKwl9IGVsc2UgaWYgKCFzdGVwX2NoYW5n ZSAmJiBzdGVwX3VzZWRfZGlmZikgewo+ICsJCS8qCj4gKwkJICogSGF2ZSBleGFjdGx5IG9uZSBj cml0aWNhbCBxd29yZCwgYWxsIHRoZSBvdGhlciBxd29yZHMgYXJlIHNldAo+ICsJCSAqIGNvcnJl Y3RseSwgc28gd2UgY2FuIHNldCB0aGlzIHF3b3JkIG5vdy4KPiArCQkgKi8KPiArCQlpID0gZmZz KHN0ZXBfdXNlZF9kaWZmKSAtIDE7Cj4gKwkJc3RlcFtpXSA9IHRhcmdldFtpXTsKPiArCX0gZWxz ZSBpZiAoIXN0ZXBfY2hhbmdlKSB7Cj4gKwkJLyogY3VyID09IHRhcmdldCwgc28gYWxsIGRvbmUg Ki8KPiArCQlpZiAobWVtY21wKGN1ciwgdGFyZ2V0LCBsZW4gKiBzaXplb2YoKmN1cikpID09IDAp Cj4gKwkJCXJldHVybiB0cnVlOwo+ICsKPiArCQkvKgo+ICsJCSAqIEFsbCB0aGUgdXNlZCBIVyBi aXRzIG1hdGNoLCBidXQgdW51c2VkIGJpdHMgYXJlIGRpZmZlcmVudC4KPiArCQkgKiBTZXQgdGhl bSBhcyB3ZWxsLiBUZWNobmljYWxseSB0aGlzIGlzbid0IG5lY2Vzc2FyeSBidXQgaXQKPiArCQkg KiBicmluZ3MgdGhlIGVudHJ5IHRvIHRoZSBmdWxsIHRhcmdldCBzdGF0ZSwgc28gaWYgdGhlcmUg YXJlCj4gKwkJICogYnVncyBpbiB0aGUgbWFzayBjYWxjdWxhdGlvbiB0aGlzIHdpbGwgb2JzY3Vy ZSB0aGVtLgo+ICsJCSAqLwo+ICsJCW1lbWNweShzdGVwLCB0YXJnZXQsIGxlbiAqIHNpemVvZigq c3RlcCkpOwo+ICsJfQo+ICsKPiArCWZvciAoaSA9IDA7IGkgIT0gbGVuOyBpKyspCj4gKwkJV1JJ VEVfT05DRShjdXJbaV0sIHN0ZXBbaV0pOwo+ICsJcmV0dXJuIGZhbHNlOwo+ICt9Cj4gKwo+ICBz dGF0aWMgdm9pZCBhcm1fc21tdV9zeW5jX2NkKHN0cnVjdCBhcm1fc21tdV9tYXN0ZXIgKm1hc3Rl ciwKPiAgCQkJICAgICBpbnQgc3NpZCwgYm9vbCBsZWFmKQo+ICB7Cj4gQEAgLTEyNDgsMzcgKzEz NDMsMTE1IEBAIHN0YXRpYyB2b2lkIGFybV9zbW11X3N5bmNfc3RlX2Zvcl9zaWQoc3RydWN0IGFy bV9zbW11X2RldmljZSAqc21tdSwgdTMyIHNpZCkKPiAgCWFybV9zbW11X2NtZHFfaXNzdWVfY21k X3dpdGhfc3luYyhzbW11LCAmY21kKTsKPiAgfQo+ICAKPiArLyoKPiArICogQmFzZWQgb24gdGhl IHZhbHVlIG9mIGVudCByZXBvcnQgd2hpY2ggYml0cyBvZiB0aGUgU1RFIHRoZSBIVyB3aWxsIGFj Y2Vzcy4gSXQKPiArICogd291bGQgYmUgbmljZSBpZiB0aGlzIHdhcyBjb21wbGV0ZSBhY2NvcmRp bmcgdG8gdGhlIHNwZWMsIGJ1dCBtaW5pbWFsbHkgaXQKPiArICogaGFzIHRvIGNhcHR1cmUgdGhl IGJpdHMgdGhpcyBkcml2ZXIgdXNlcy4KPiArICovCj4gK3N0YXRpYyB2b2lkIGFybV9zbW11X2dl dF9zdGVfdXNlZChjb25zdCBzdHJ1Y3QgYXJtX3NtbXVfc3RlICplbnQsCj4gKwkJCQkgIHN0cnVj dCBhcm1fc21tdV9zdGUgKnVzZWRfYml0cykKPiArewo+ICsJbWVtc2V0KHVzZWRfYml0cywgMCwg c2l6ZW9mKCp1c2VkX2JpdHMpKTsKPiArCj4gKwl1c2VkX2JpdHMtPmRhdGFbMF0gPSBjcHVfdG9f bGU2NChTVFJUQUJfU1RFXzBfVik7Cj4gKwlpZiAoIShlbnQtPmRhdGFbMF0gJiBjcHVfdG9fbGU2 NChTVFJUQUJfU1RFXzBfVikpKQo+ICsJCXJldHVybjsKPiArCj4gKwkvKgo+ICsJICogSWYgUzEg aXMgZW5hYmxlZCBTMURTUyBpcyB2YWxpZCwgc2VlIDEzLjUgU3VtbWFyeSBvZgo+ICsJICogYXR0 cmlidXRlL3Blcm1pc3Npb24gY29uZmlndXJhdGlvbiBmaWVsZHMgZm9yIHRoZSBTSENGRyBiZWhh dmlvci4KPiArCSAqLwo+ICsJaWYgKEZJRUxEX0dFVChTVFJUQUJfU1RFXzBfQ0ZHLCBsZTY0X3Rv X2NwdShlbnQtPmRhdGFbMF0pKSAmIDEgJiYKPiArCSAgICBGSUVMRF9HRVQoU1RSVEFCX1NURV8x X1MxRFNTLCBsZTY0X3RvX2NwdShlbnQtPmRhdGFbMV0pKSA9PQo+ICsJCSAgICBTVFJUQUJfU1RF XzFfUzFEU1NfQllQQVNTKQo+ICsJCXVzZWRfYml0cy0+ZGF0YVsxXSB8PSBjcHVfdG9fbGU2NChT VFJUQUJfU1RFXzFfU0hDRkcpOwo+ICsKPiArCXVzZWRfYml0cy0+ZGF0YVswXSB8PSBjcHVfdG9f bGU2NChTVFJUQUJfU1RFXzBfQ0ZHKTsKPiArCXN3aXRjaCAoRklFTERfR0VUKFNUUlRBQl9TVEVf MF9DRkcsIGxlNjRfdG9fY3B1KGVudC0+ZGF0YVswXSkpKSB7Cj4gKwljYXNlIFNUUlRBQl9TVEVf MF9DRkdfQUJPUlQ6Cj4gKwkJYnJlYWs7Cj4gKwljYXNlIFNUUlRBQl9TVEVfMF9DRkdfQllQQVNT Ogo+ICsJCXVzZWRfYml0cy0+ZGF0YVsxXSB8PSBjcHVfdG9fbGU2NChTVFJUQUJfU1RFXzFfU0hD RkcpOwo+ICsJCWJyZWFrOwo+ICsJY2FzZSBTVFJUQUJfU1RFXzBfQ0ZHX1MxX1RSQU5TOgo+ICsJ CXVzZWRfYml0cy0+ZGF0YVswXSB8PSBjcHVfdG9fbGU2NChTVFJUQUJfU1RFXzBfUzFGTVQgfAo+ ICsJCQkJCQkgIFNUUlRBQl9TVEVfMF9TMUNUWFBUUl9NQVNLIHwKPiArCQkJCQkJICBTVFJUQUJf U1RFXzBfUzFDRE1BWCk7Cj4gKwkJdXNlZF9iaXRzLT5kYXRhWzFdIHw9Cj4gKwkJCWNwdV90b19s ZTY0KFNUUlRBQl9TVEVfMV9TMURTUyB8IFNUUlRBQl9TVEVfMV9TMUNJUiB8Cj4gKwkJCQkgICAg U1RSVEFCX1NURV8xX1MxQ09SIHwgU1RSVEFCX1NURV8xX1MxQ1NIIHwKPiArCQkJCSAgICBTVFJU QUJfU1RFXzFfUzFTVEFMTEQgfCBTVFJUQUJfU1RFXzFfU1RSVyk7Cj4gKwkJdXNlZF9iaXRzLT5k YXRhWzFdIHw9IGNwdV90b19sZTY0KFNUUlRBQl9TVEVfMV9FQVRTKTsKPiArCQlicmVhazsKQUZB SVUsIHRoaXMgaXMgbWlzc2luZyBzb21ldGhpbmcgbGlrZSAod2hpbGUgcGFzc2luZyBzbW11LT5m ZWF0dXJlcykKCXVzZWRfYml0cy0+ZGF0YVsyXSB8PSBmZWF0dXJlcyAmIEFSTV9TTU1VX0ZFQVRf TkVTVElORyA/CgkJCSAgICAgIGNwdV90b19sZTY0KFNUUlRBQl9TVEVfMl9TMlZNSUQpIDogMDsK CkFzIHRoZSBTTU1VdjMgbWFudWFsIHNheXM6CuKAnCBGb3IgYSBOb24tc2VjdXJlIFNURSB3aGVu IHN0YWdlIDIgaXMgaW1wbGVtZW50ZWQgKFNNTVVfSURSMC5TMlAgPT0gMSkKICB0cmFuc2xhdGlv bnMgcmVzdWx0aW5nIGZyb20gYSBTdHJlYW1Xb3JsZCA9PSBOUy1FTDEgY29uZmlndXJhdGlvbiBh cmUKICBWTUlELXRhZ2dlZCB3aXRoIFMyVk1JRCB3aGVuIGVpdGhlciBvZiBzdGFnZSAxIChDb25m aWdbMF0gPT0gMSkgb3Igc3RhZ2UgMgogIChDb25maWdbMV0gPT0gMSkgcHJvdmlkZSB0cmFuc2xh dGlvbi7igJwKCldoaWNoIG1lYW5zIGluIGNhc2Ugb2YgUzE9PlMyIHN3aXRjaCBvciB2aWNlIHZl cnNhIHRoaXMgYWxnb3JpdGhtIHdpbGwgaWdub3JlClZNSUQgd2hpbGUgaXQgaXMgdXNlZC4KCj4g KwljYXNlIFNUUlRBQl9TVEVfMF9DRkdfUzJfVFJBTlM6Cj4gKwkJdXNlZF9iaXRzLT5kYXRhWzFd IHw9Cj4gKwkJCWNwdV90b19sZTY0KFNUUlRBQl9TVEVfMV9FQVRTIHwgU1RSVEFCX1NURV8xX1NI Q0ZHKTsKPiArCQl1c2VkX2JpdHMtPmRhdGFbMl0gfD0KPiArCQkJY3B1X3RvX2xlNjQoU1RSVEFC X1NURV8yX1MyVk1JRCB8IFNUUlRBQl9TVEVfMl9WVENSIHwKPiArCQkJCSAgICBTVFJUQUJfU1RF XzJfUzJBQTY0IHwgU1RSVEFCX1NURV8yX1MyRU5ESSB8Cj4gKwkJCQkgICAgU1RSVEFCX1NURV8y X1MyUFRXIHwgU1RSVEFCX1NURV8yX1MyUik7Cj4gKwkJdXNlZF9iaXRzLT5kYXRhWzNdIHw9IGNw dV90b19sZTY0KFNUUlRBQl9TVEVfM19TMlRUQl9NQVNLKTsKPiArCQlicmVhazsKPiArCj4gKwlk ZWZhdWx0Ogo+ICsJCW1lbXNldCh1c2VkX2JpdHMsIDB4RkYsIHNpemVvZigqdXNlZF9iaXRzKSk7 Cj4gKwkJV0FSTl9PTih0cnVlKTsKPiArCX0KPiArfQo+ICsKPiArc3RhdGljIGJvb2wgYXJtX3Nt bXVfd3JpdGVfc3RlX3N0ZXAoc3RydWN0IGFybV9zbW11X3N0ZSAqY3VyLAo+ICsJCQkJICAgIGNv bnN0IHN0cnVjdCBhcm1fc21tdV9zdGUgKnRhcmdldCwKPiArCQkJCSAgICBjb25zdCBzdHJ1Y3Qg YXJtX3NtbXVfc3RlICp0YXJnZXRfdXNlZCkKPiArewo+ICsJc3RydWN0IGFybV9zbW11X3N0ZSBj dXJfdXNlZDsKPiArCXN0cnVjdCBhcm1fc21tdV9zdGUgc3RlcDsKPiArCj4gKwlhcm1fc21tdV9n ZXRfc3RlX3VzZWQoY3VyLCAmY3VyX3VzZWQpOwo+ICsJcmV0dXJuIGFybV9zbW11X3dyaXRlX2Vu dHJ5X3N0ZXAoY3VyLT5kYXRhLCBjdXJfdXNlZC5kYXRhLCB0YXJnZXQtPmRhdGEsCj4gKwkJCQkJ IHRhcmdldF91c2VkLT5kYXRhLCBzdGVwLmRhdGEsCj4gKwkJCQkJIGNwdV90b19sZTY0KFNUUlRB Ql9TVEVfMF9WKSwKPiArCQkJCQkgQVJSQVlfU0laRShjdXItPmRhdGEpKTsKPiArfQo+ICsKPiAr c3RhdGljIHZvaWQgYXJtX3NtbXVfd3JpdGVfc3RlKHN0cnVjdCBhcm1fc21tdV9kZXZpY2UgKnNt bXUsIHUzMiBzaWQsCj4gKwkJCSAgICAgICBzdHJ1Y3QgYXJtX3NtbXVfc3RlICpzdGUsCj4gKwkJ CSAgICAgICBjb25zdCBzdHJ1Y3QgYXJtX3NtbXVfc3RlICp0YXJnZXQpCj4gK3sKPiArCXN0cnVj dCBhcm1fc21tdV9zdGUgdGFyZ2V0X3VzZWQ7Cj4gKwlpbnQgaTsKPiArCj4gKwlhcm1fc21tdV9n ZXRfc3RlX3VzZWQodGFyZ2V0LCAmdGFyZ2V0X3VzZWQpOwo+ICsJLyogTWFza3MgaW4gYXJtX3Nt bXVfZ2V0X3N0ZV91c2VkKCkgYXJlIHVwIHRvIGRhdGUgKi8KPiArCWZvciAoaSA9IDA7IGkgIT0g QVJSQVlfU0laRSh0YXJnZXQtPmRhdGEpOyBpKyspCj4gKwkJV0FSTl9PTl9PTkNFKHRhcmdldC0+ ZGF0YVtpXSAmIH50YXJnZXRfdXNlZC5kYXRhW2ldKTsKSW4gd2hhdCBzaXR1YXRpb24gdGhpcyB3 b3VsZCBiZSB0cmlnZ2VyZWQsIGlzIHRoYXQgZm9yIGZ1dHVyZSBwcm9vZmluZywKbWF5YmUgd2Ug Y2FuIG1vdmUgaXQgdG8gYXJtX3NtbXVfZ2V0X3N0ZV91c2VkKCk/Cgo+ICsKPiArCXdoaWxlICh0 cnVlKSB7Cj4gKwkJaWYgKGFybV9zbW11X3dyaXRlX3N0ZV9zdGVwKHN0ZSwgdGFyZ2V0LCAmdGFy Z2V0X3VzZWQpKQo+ICsJCQlicmVhazsKPiArCQlhcm1fc21tdV9zeW5jX3N0ZV9mb3Jfc2lkKHNt bXUsIHNpZCk7Cj4gKwl9Cj4gKwo+ICsJLyogSXQncyBsaWtlbHkgdGhhdCB3ZSdsbCB3YW50IHRv IHVzZSB0aGUgbmV3IFNURSBzb29uICovCj4gKwlpZiAoIShzbW11LT5vcHRpb25zICYgQVJNX1NN TVVfT1BUX1NLSVBfUFJFRkVUQ0gpKSB7Cj4gKwkJc3RydWN0IGFybV9zbW11X2NtZHFfZW50Cj4g KwkJCXByZWZldGNoX2NtZCA9IHsgLm9wY29kZSA9IENNRFFfT1BfUFJFRkVUQ0hfQ0ZHLAo+ICsJ CQkJCSAucHJlZmV0Y2ggPSB7Cj4gKwkJCQkJCSAuc2lkID0gc2lkLAo+ICsJCQkJCSB9IH07Cj4g Kwo+ICsJCWFybV9zbW11X2NtZHFfaXNzdWVfY21kKHNtbXUsICZwcmVmZXRjaF9jbWQpOwo+ICsJ fQo+ICt9Cj4gKwo+ICBzdGF0aWMgdm9pZCBhcm1fc21tdV93cml0ZV9zdHJ0YWJfZW50KHN0cnVj dCBhcm1fc21tdV9tYXN0ZXIgKm1hc3RlciwgdTMyIHNpZCwKPiAgCQkJCSAgICAgIHN0cnVjdCBh cm1fc21tdV9zdGUgKmRzdCkKPiAgewo+IC0JLyoKPiAtCSAqIFRoaXMgaXMgaGlkZW91c2x5IGNv bXBsaWNhdGVkLCBidXQgd2Ugb25seSByZWFsbHkgY2FyZSBhYm91dAo+IC0JICogdGhyZWUgY2Fz ZXMgYXQgdGhlIG1vbWVudDoKPiAtCSAqCj4gLQkgKiAxLiBJbnZhbGlkIChhbGwgemVybykgLT4g YnlwYXNzL2ZhdWx0IChpbml0KQo+IC0JICogMi4gQnlwYXNzL2ZhdWx0IC0+IHRyYW5zbGF0aW9u L2J5cGFzcyAoYXR0YWNoKQo+IC0JICogMy4gVHJhbnNsYXRpb24vYnlwYXNzIC0+IGJ5cGFzcy9m YXVsdCAoZGV0YWNoKQo+IC0JICoKPiAtCSAqIEdpdmVuIHRoYXQgd2UgY2FuJ3QgdXBkYXRlIHRo ZSBTVEUgYXRvbWljYWxseSBhbmQgdGhlIFNNTVUKPiAtCSAqIGRvZXNuJ3QgcmVhZCB0aGUgdGhp bmcgaW4gYSBkZWZpbmVkIG9yZGVyLCB0aGF0IGxlYXZlcyB1cwo+IC0JICogd2l0aCB0aGUgZm9s bG93aW5nIG1haW50ZW5hbmNlIHJlcXVpcmVtZW50czoKPiAtCSAqCj4gLQkgKiAxLiBVcGRhdGUg Q29uZmlnLCByZXR1cm4gKGluaXQgdGltZSBTVEVzIGFyZW4ndCBsaXZlKQo+IC0JICogMi4gV3Jp dGUgZXZlcnl0aGluZyBhcGFydCBmcm9tIGR3b3JkIDAsIHN5bmMsIHdyaXRlIGR3b3JkIDAsIHN5 bmMKPiAtCSAqIDMuIFVwZGF0ZSBDb25maWcsIHN5bmMKPiAtCSAqLwo+IC0JdTY0IHZhbCA9IGxl NjRfdG9fY3B1KGRzdC0+ZGF0YVswXSk7Cj4gLQlib29sIHN0ZV9saXZlID0gZmFsc2U7Cj4gKwl1 NjQgdmFsOwo+ICAJc3RydWN0IGFybV9zbW11X2RldmljZSAqc21tdSA9IG1hc3Rlci0+c21tdTsK PiAgCXN0cnVjdCBhcm1fc21tdV9jdHhfZGVzY19jZmcgKmNkX3RhYmxlID0gTlVMTDsKPiAgCXN0 cnVjdCBhcm1fc21tdV9zMl9jZmcgKnMyX2NmZyA9IE5VTEw7Cj4gIAlzdHJ1Y3QgYXJtX3NtbXVf ZG9tYWluICpzbW11X2RvbWFpbiA9IG1hc3Rlci0+ZG9tYWluOwo+IC0Jc3RydWN0IGFybV9zbW11 X2NtZHFfZW50IHByZWZldGNoX2NtZCA9IHsKPiAtCQkub3Bjb2RlCQk9IENNRFFfT1BfUFJFRkVU Q0hfQ0ZHLAo+IC0JCS5wcmVmZXRjaAk9IHsKPiAtCQkJLnNpZAk9IHNpZCwKPiAtCQl9LAo+IC0J fTsKPiArCXN0cnVjdCBhcm1fc21tdV9zdGUgdGFyZ2V0ID0ge307Cj4gIAo+ICAJaWYgKHNtbXVf ZG9tYWluKSB7Cj4gIAkJc3dpdGNoIChzbW11X2RvbWFpbi0+c3RhZ2UpIHsKPiBAQCAtMTI5Mywy MiArMTQ2Niw2IEBAIHN0YXRpYyB2b2lkIGFybV9zbW11X3dyaXRlX3N0cnRhYl9lbnQoc3RydWN0 IGFybV9zbW11X21hc3RlciAqbWFzdGVyLCB1MzIgc2lkLAo+ICAJCX0KPiAgCX0KPiAgCj4gLQlp ZiAodmFsICYgU1RSVEFCX1NURV8wX1YpIHsKPiAtCQlzd2l0Y2ggKEZJRUxEX0dFVChTVFJUQUJf U1RFXzBfQ0ZHLCB2YWwpKSB7Cj4gLQkJY2FzZSBTVFJUQUJfU1RFXzBfQ0ZHX0JZUEFTUzoKPiAt CQkJYnJlYWs7Cj4gLQkJY2FzZSBTVFJUQUJfU1RFXzBfQ0ZHX1MxX1RSQU5TOgo+IC0JCWNhc2Ug U1RSVEFCX1NURV8wX0NGR19TMl9UUkFOUzoKPiAtCQkJc3RlX2xpdmUgPSB0cnVlOwo+IC0JCQli cmVhazsKPiAtCQljYXNlIFNUUlRBQl9TVEVfMF9DRkdfQUJPUlQ6Cj4gLQkJCUJVR19PTighZGlz YWJsZV9ieXBhc3MpOwo+IC0JCQlicmVhazsKPiAtCQlkZWZhdWx0Ogo+IC0JCQlCVUcoKTsgLyog U1RFIGNvcnJ1cHRpb24gKi8KPiAtCQl9Cj4gLQl9Cj4gLQo+ICAJLyogTnVrZSB0aGUgZXhpc3Rp bmcgU1RFXzAgdmFsdWUsIGFzIHdlJ3JlIGdvaW5nIHRvIHJld3JpdGUgaXQgKi8KPiAgCXZhbCA9 IFNUUlRBQl9TVEVfMF9WOwo+ICAKPiBAQCAtMTMxOSwxNiArMTQ3NiwxMSBAQCBzdGF0aWMgdm9p ZCBhcm1fc21tdV93cml0ZV9zdHJ0YWJfZW50KHN0cnVjdCBhcm1fc21tdV9tYXN0ZXIgKm1hc3Rl ciwgdTMyIHNpZCwKPiAgCQllbHNlCj4gIAkJCXZhbCB8PSBGSUVMRF9QUkVQKFNUUlRBQl9TVEVf MF9DRkcsIFNUUlRBQl9TVEVfMF9DRkdfQllQQVNTKTsKPiAgCj4gLQkJZHN0LT5kYXRhWzBdID0g Y3B1X3RvX2xlNjQodmFsKTsKPiAtCQlkc3QtPmRhdGFbMV0gPSBjcHVfdG9fbGU2NChGSUVMRF9Q UkVQKFNUUlRBQl9TVEVfMV9TSENGRywKPiArCQl0YXJnZXQuZGF0YVswXSA9IGNwdV90b19sZTY0 KHZhbCk7Cj4gKwkJdGFyZ2V0LmRhdGFbMV0gPSBjcHVfdG9fbGU2NChGSUVMRF9QUkVQKFNUUlRB Ql9TVEVfMV9TSENGRywKPiAgCQkJCQkJU1RSVEFCX1NURV8xX1NIQ0ZHX0lOQ09NSU5HKSk7Cj4g LQkJZHN0LT5kYXRhWzJdID0gMDsgLyogTnVrZSB0aGUgVk1JRCAqLwo+IC0JCS8qCj4gLQkJICog VGhlIFNNTVUgY2FuIHBlcmZvcm0gbmVnYXRpdmUgY2FjaGluZywgc28gd2UgbXVzdCBzeW5jCj4g LQkJICogdGhlIFNURSByZWdhcmRsZXNzIG9mIHdoZXRoZXIgdGhlIG9sZCB2YWx1ZSB3YXMgbGl2 ZS4KPiAtCQkgKi8KPiAtCQlpZiAoc21tdSkKPiAtCQkJYXJtX3NtbXVfc3luY19zdGVfZm9yX3Np ZChzbW11LCBzaWQpOwo+ICsJCXRhcmdldC5kYXRhWzJdID0gMDsgLyogTnVrZSB0aGUgVk1JRCAq Lwo+ICsJCWFybV9zbW11X3dyaXRlX3N0ZShzbW11LCBzaWQsIGRzdCwgJnRhcmdldCk7Cj4gIAkJ cmV0dXJuOwo+ICAJfQo+ICAKPiBAQCAtMTMzNiw4ICsxNDg4LDcgQEAgc3RhdGljIHZvaWQgYXJt X3NtbXVfd3JpdGVfc3RydGFiX2VudChzdHJ1Y3QgYXJtX3NtbXVfbWFzdGVyICptYXN0ZXIsIHUz MiBzaWQsCj4gIAkJdTY0IHN0cncgPSBzbW11LT5mZWF0dXJlcyAmIEFSTV9TTU1VX0ZFQVRfRTJI ID8KPiAgCQkJU1RSVEFCX1NURV8xX1NUUldfRUwyIDogU1RSVEFCX1NURV8xX1NUUldfTlNFTDE7 Cj4gIAo+IC0JCUJVR19PTihzdGVfbGl2ZSk7Cj4gLQkJZHN0LT5kYXRhWzFdID0gY3B1X3RvX2xl NjQoCj4gKwkJdGFyZ2V0LmRhdGFbMV0gPSBjcHVfdG9fbGU2NCgKPiAgCQkJIEZJRUxEX1BSRVAo U1RSVEFCX1NURV8xX1MxRFNTLCBTVFJUQUJfU1RFXzFfUzFEU1NfU1NJRDApIHwKPiAgCQkJIEZJ RUxEX1BSRVAoU1RSVEFCX1NURV8xX1MxQ0lSLCBTVFJUQUJfU1RFXzFfUzFDX0NBQ0hFX1dCUkEp IHwKPiAgCQkJIEZJRUxEX1BSRVAoU1RSVEFCX1NURV8xX1MxQ09SLCBTVFJUQUJfU1RFXzFfUzFD X0NBQ0hFX1dCUkEpIHwKPiBAQCAtMTM0Niw3ICsxNDk3LDcgQEAgc3RhdGljIHZvaWQgYXJtX3Nt bXVfd3JpdGVfc3RydGFiX2VudChzdHJ1Y3QgYXJtX3NtbXVfbWFzdGVyICptYXN0ZXIsIHUzMiBz aWQsCj4gIAo+ICAJCWlmIChzbW11LT5mZWF0dXJlcyAmIEFSTV9TTU1VX0ZFQVRfU1RBTExTICYm Cj4gIAkJICAgICFtYXN0ZXItPnN0YWxsX2VuYWJsZWQpCj4gLQkJCWRzdC0+ZGF0YVsxXSB8PSBj cHVfdG9fbGU2NChTVFJUQUJfU1RFXzFfUzFTVEFMTEQpOwo+ICsJCQl0YXJnZXQuZGF0YVsxXSB8 PSBjcHVfdG9fbGU2NChTVFJUQUJfU1RFXzFfUzFTVEFMTEQpOwo+ICAKPiAgCQl2YWwgfD0gKGNk X3RhYmxlLT5jZHRhYl9kbWEgJiBTVFJUQUJfU1RFXzBfUzFDVFhQVFJfTUFTSykgfAo+ICAJCQlG SUVMRF9QUkVQKFNUUlRBQl9TVEVfMF9DRkcsIFNUUlRBQl9TVEVfMF9DRkdfUzFfVFJBTlMpIHwK PiBAQCAtMTM1NSw4ICsxNTA2LDcgQEAgc3RhdGljIHZvaWQgYXJtX3NtbXVfd3JpdGVfc3RydGFi X2VudChzdHJ1Y3QgYXJtX3NtbXVfbWFzdGVyICptYXN0ZXIsIHUzMiBzaWQsCj4gIAl9Cj4gIAo+ ICAJaWYgKHMyX2NmZykgewo+IC0JCUJVR19PTihzdGVfbGl2ZSk7Cj4gLQkJZHN0LT5kYXRhWzJd ID0gY3B1X3RvX2xlNjQoCj4gKwkJdGFyZ2V0LmRhdGFbMl0gPSBjcHVfdG9fbGU2NCgKPiAgCQkJ IEZJRUxEX1BSRVAoU1RSVEFCX1NURV8yX1MyVk1JRCwgczJfY2ZnLT52bWlkKSB8Cj4gIAkJCSBG SUVMRF9QUkVQKFNUUlRBQl9TVEVfMl9WVENSLCBzMl9jZmctPnZ0Y3IpIHwKPiAgI2lmZGVmIF9f QklHX0VORElBTgo+IEBAIC0xMzY1LDIzICsxNTE1LDE3IEBAIHN0YXRpYyB2b2lkIGFybV9zbW11 X3dyaXRlX3N0cnRhYl9lbnQoc3RydWN0IGFybV9zbW11X21hc3RlciAqbWFzdGVyLCB1MzIgc2lk LAo+ICAJCQkgU1RSVEFCX1NURV8yX1MyUFRXIHwgU1RSVEFCX1NURV8yX1MyQUE2NCB8Cj4gIAkJ CSBTVFJUQUJfU1RFXzJfUzJSKTsKPiAgCj4gLQkJZHN0LT5kYXRhWzNdID0gY3B1X3RvX2xlNjQo czJfY2ZnLT52dHRiciAmIFNUUlRBQl9TVEVfM19TMlRUQl9NQVNLKTsKPiArCQl0YXJnZXQuZGF0 YVszXSA9IGNwdV90b19sZTY0KHMyX2NmZy0+dnR0YnIgJiBTVFJUQUJfU1RFXzNfUzJUVEJfTUFT Syk7Cj4gIAo+ICAJCXZhbCB8PSBGSUVMRF9QUkVQKFNUUlRBQl9TVEVfMF9DRkcsIFNUUlRBQl9T VEVfMF9DRkdfUzJfVFJBTlMpOwo+ICAJfQo+ICAKPiAgCWlmIChtYXN0ZXItPmF0c19lbmFibGVk KQo+IC0JCWRzdC0+ZGF0YVsxXSB8PSBjcHVfdG9fbGU2NChGSUVMRF9QUkVQKFNUUlRBQl9TVEVf MV9FQVRTLAo+ICsJCXRhcmdldC5kYXRhWzFdIHw9IGNwdV90b19sZTY0KEZJRUxEX1BSRVAoU1RS VEFCX1NURV8xX0VBVFMsCj4gIAkJCQkJCSBTVFJUQUJfU1RFXzFfRUFUU19UUkFOUykpOwo+ICAK PiAtCWFybV9zbW11X3N5bmNfc3RlX2Zvcl9zaWQoc21tdSwgc2lkKTsKPiAtCS8qIFNlZSBjb21t ZW50IGluIGFybV9zbW11X3dyaXRlX2N0eF9kZXNjKCkgKi8KPiAtCVdSSVRFX09OQ0UoZHN0LT5k YXRhWzBdLCBjcHVfdG9fbGU2NCh2YWwpKTsKPiAtCWFybV9zbW11X3N5bmNfc3RlX2Zvcl9zaWQo c21tdSwgc2lkKTsKPiAtCj4gLQkvKiBJdCdzIGxpa2VseSB0aGF0IHdlJ2xsIHdhbnQgdG8gdXNl IHRoZSBuZXcgU1RFIHNvb24gKi8KPiAtCWlmICghKHNtbXUtPm9wdGlvbnMgJiBBUk1fU01NVV9P UFRfU0tJUF9QUkVGRVRDSCkpCj4gLQkJYXJtX3NtbXVfY21kcV9pc3N1ZV9jbWQoc21tdSwgJnBy ZWZldGNoX2NtZCk7Cj4gKwl0YXJnZXQuZGF0YVswXSA9IGNwdV90b19sZTY0KHZhbCk7Cj4gKwlh cm1fc21tdV93cml0ZV9zdGUoc21tdSwgc2lkLCBkc3QsICZ0YXJnZXQpOwo+ICB9Cj4gIAo+ICBz dGF0aWMgdm9pZCBhcm1fc21tdV9pbml0X2J5cGFzc19zdGVzKHN0cnVjdCBhcm1fc21tdV9zdGUg KnN0cnRhYiwKPiAtLSAKPiAyLjQzLjAKPgpUaGFua3MsCk1vc3RhZmEKCl9fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmxpbnV4LWFybS1rZXJuZWwgbWFpbGlu ZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMu aW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LWFybS1rZXJuZWwK