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charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240128212515.630345-4-andrealmeid@igalia.com> X-Operating-System: Linux phenom 6.6.11-amd64 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel@ffwll.ch, 'Marek =?utf-8?B?T2zFocOhayc=?= , Michel =?iso-8859-1?Q?D=E4nzer?= , Simon Ser , linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, Xaver Hugl , Pekka Paalanen , dri-devel@lists.freedesktop.org, kernel-dev@igalia.com, alexander.deucher@amd.com, Joshua Ashton , Daniel Stone , Dave Airlie , christian.koenig@amd.com, ville.syrjala@linux.intel.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Sun, Jan 28, 2024 at 06:25:15PM -0300, André Almeida wrote: > AMD GPUs can do async flips with changes on more properties than just > the FB ID, so implement a custom check_async_props for AMD planes. > > Allow amdgpu to do async flips with overlay planes as well. > > Signed-off-by: André Almeida > --- > v3: allow overlay planes This comment very much written with a lack of clearly better ideas, but: Do we really need this much flexibility, especially for the first driver adding the first few additional properties? A simple bool on struct drm_plane to indicate whether async flips are ok or not should also do this job here? Maybe a bit of work to roll that out to the primary planes for current drivers, but not much. And wouldn't need drivers to implement some very uapi-marshalling atomic code ... Also we could probably remove the current drm_mode_config.async_flip flag and entirely replace it with the per-plane one. -Sima > > .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 29 +++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c > index 116121e647ca..ed75b69636b4 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c > @@ -25,6 +25,7 @@ > */ > > #include > +#include > #include > #include > #include > @@ -1430,6 +1431,33 @@ static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane, > drm_atomic_helper_plane_destroy_state(plane, state); > } > > +static int amdgpu_dm_plane_check_async_props(struct drm_property *prop, > + struct drm_plane *plane, > + struct drm_plane_state *plane_state, > + struct drm_mode_object *obj, > + u64 prop_value, u64 old_val) > +{ > + struct drm_mode_config *config = &plane->dev->mode_config; > + int ret; > + > + if (prop != config->prop_fb_id && > + prop != config->prop_in_fence_fd) { > + ret = drm_atomic_plane_get_property(plane, plane_state, > + prop, &old_val); > + return drm_atomic_check_prop_changes(ret, old_val, prop_value, prop); > + } > + > + if (plane_state->plane->type != DRM_PLANE_TYPE_PRIMARY && > + plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) { > + drm_dbg_atomic(prop->dev, > + "[OBJECT:%d] Only primary or overlay planes can be changed during async flip\n", > + obj->id); > + return -EINVAL; > + } > + > + return 0; > +} > + > static const struct drm_plane_funcs dm_plane_funcs = { > .update_plane = drm_atomic_helper_update_plane, > .disable_plane = drm_atomic_helper_disable_plane, > @@ -1438,6 +1466,7 @@ static const struct drm_plane_funcs dm_plane_funcs = { > .atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state, > .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state, > .format_mod_supported = amdgpu_dm_plane_format_mod_supported, > + .check_async_props = amdgpu_dm_plane_check_async_props, > }; > > int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, > -- > 2.43.0 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42D33C46CD2 for ; Tue, 30 Jan 2024 10:57:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7DEEE10F791; Tue, 30 Jan 2024 10:57:14 +0000 (UTC) Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) by gabe.freedesktop.org (Postfix) with ESMTPS id 17631112EB7 for ; Tue, 30 Jan 2024 10:57:13 +0000 (UTC) Received: by mail-ed1-f44.google.com with SMTP id 4fb4d7f45d1cf-5586764bd0aso1308803a12.0 for ; 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Tue, 30 Jan 2024 02:56:11 -0800 (PST) Received: from phenom.ffwll.local ([2a02:168:57f4:0:efd0:b9e5:5ae6:c2fa]) by smtp.gmail.com with ESMTPSA id ss6-20020a170907c00600b00a3535b76c42sm4058309ejc.15.2024.01.30.02.56.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 02:56:10 -0800 (PST) Date: Tue, 30 Jan 2024 11:56:08 +0100 From: Daniel Vetter To: =?iso-8859-1?Q?Andr=E9?= Almeida Subject: Re: [PATCH v3 3/3] drm/amdgpu: Implement check_async_props for planes Message-ID: Mail-Followup-To: =?iso-8859-1?Q?Andr=E9?= Almeida , dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, kernel-dev@igalia.com, alexander.deucher@amd.com, christian.koenig@amd.com, Simon Ser , Pekka Paalanen , Daniel Stone , 'Marek =?utf-8?B?T2zFocOhayc=?= , Dave Airlie , ville.syrjala@linux.intel.com, Xaver Hugl , Joshua Ashton , Michel =?iso-8859-1?Q?D=E4nzer?= References: <20240128212515.630345-1-andrealmeid@igalia.com> <20240128212515.630345-4-andrealmeid@igalia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240128212515.630345-4-andrealmeid@igalia.com> X-Operating-System: Linux phenom 6.6.11-amd64 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel@ffwll.ch, 'Marek =?utf-8?B?T2zFocOhayc=?= , Michel =?iso-8859-1?Q?D=E4nzer?= , linux-kernel@vger.kernel.org, amd-gfx@lists.freedesktop.org, Xaver Hugl , Pekka Paalanen , dri-devel@lists.freedesktop.org, kernel-dev@igalia.com, alexander.deucher@amd.com, Joshua Ashton , Dave Airlie , christian.koenig@amd.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Sun, Jan 28, 2024 at 06:25:15PM -0300, André Almeida wrote: > AMD GPUs can do async flips with changes on more properties than just > the FB ID, so implement a custom check_async_props for AMD planes. > > Allow amdgpu to do async flips with overlay planes as well. > > Signed-off-by: André Almeida > --- > v3: allow overlay planes This comment very much written with a lack of clearly better ideas, but: Do we really need this much flexibility, especially for the first driver adding the first few additional properties? A simple bool on struct drm_plane to indicate whether async flips are ok or not should also do this job here? Maybe a bit of work to roll that out to the primary planes for current drivers, but not much. And wouldn't need drivers to implement some very uapi-marshalling atomic code ... Also we could probably remove the current drm_mode_config.async_flip flag and entirely replace it with the per-plane one. -Sima > > .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 29 +++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c > index 116121e647ca..ed75b69636b4 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c > @@ -25,6 +25,7 @@ > */ > > #include > +#include > #include > #include > #include > @@ -1430,6 +1431,33 @@ static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane, > drm_atomic_helper_plane_destroy_state(plane, state); > } > > +static int amdgpu_dm_plane_check_async_props(struct drm_property *prop, > + struct drm_plane *plane, > + struct drm_plane_state *plane_state, > + struct drm_mode_object *obj, > + u64 prop_value, u64 old_val) > +{ > + struct drm_mode_config *config = &plane->dev->mode_config; > + int ret; > + > + if (prop != config->prop_fb_id && > + prop != config->prop_in_fence_fd) { > + ret = drm_atomic_plane_get_property(plane, plane_state, > + prop, &old_val); > + return drm_atomic_check_prop_changes(ret, old_val, prop_value, prop); > + } > + > + if (plane_state->plane->type != DRM_PLANE_TYPE_PRIMARY && > + plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) { > + drm_dbg_atomic(prop->dev, > + "[OBJECT:%d] Only primary or overlay planes can be changed during async flip\n", > + obj->id); > + return -EINVAL; > + } > + > + return 0; > +} > + > static const struct drm_plane_funcs dm_plane_funcs = { > .update_plane = drm_atomic_helper_update_plane, > .disable_plane = drm_atomic_helper_disable_plane, > @@ -1438,6 +1466,7 @@ static const struct drm_plane_funcs dm_plane_funcs = { > .atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state, > .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state, > .format_mod_supported = amdgpu_dm_plane_format_mod_supported, > + .check_async_props = amdgpu_dm_plane_check_async_props, > }; > > int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, > -- > 2.43.0 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71FFD29CFB for ; Tue, 30 Jan 2024 10:56:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.42 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706612178; cv=none; b=jGsF5RAMrzlJaLmJgqVmAsQjcxovqdeTos0/Kqri5Ie7tisf7tvy+PenWkN9niDc2NfJzYTgyHMaCoDy0/RhFyyaQp08kY5E9P9xGuqF8Z9snvzFDyCGmXQIf9NjU6Y3DYtlOlwubC9uYo5fq6FHY/DXjQNYs9mwujQcBWByAh0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706612178; c=relaxed/simple; bh=BfiJWrE6ge/vnnmeUJM2IZxZs4Py6umUcGQdMckRwys=; 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charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240128212515.630345-4-andrealmeid@igalia.com> X-Operating-System: Linux phenom 6.6.11-amd64 On Sun, Jan 28, 2024 at 06:25:15PM -0300, André Almeida wrote: > AMD GPUs can do async flips with changes on more properties than just > the FB ID, so implement a custom check_async_props for AMD planes. > > Allow amdgpu to do async flips with overlay planes as well. > > Signed-off-by: André Almeida > --- > v3: allow overlay planes This comment very much written with a lack of clearly better ideas, but: Do we really need this much flexibility, especially for the first driver adding the first few additional properties? A simple bool on struct drm_plane to indicate whether async flips are ok or not should also do this job here? Maybe a bit of work to roll that out to the primary planes for current drivers, but not much. And wouldn't need drivers to implement some very uapi-marshalling atomic code ... Also we could probably remove the current drm_mode_config.async_flip flag and entirely replace it with the per-plane one. -Sima > > .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 29 +++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c > index 116121e647ca..ed75b69636b4 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c > @@ -25,6 +25,7 @@ > */ > > #include > +#include > #include > #include > #include > @@ -1430,6 +1431,33 @@ static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane, > drm_atomic_helper_plane_destroy_state(plane, state); > } > > +static int amdgpu_dm_plane_check_async_props(struct drm_property *prop, > + struct drm_plane *plane, > + struct drm_plane_state *plane_state, > + struct drm_mode_object *obj, > + u64 prop_value, u64 old_val) > +{ > + struct drm_mode_config *config = &plane->dev->mode_config; > + int ret; > + > + if (prop != config->prop_fb_id && > + prop != config->prop_in_fence_fd) { > + ret = drm_atomic_plane_get_property(plane, plane_state, > + prop, &old_val); > + return drm_atomic_check_prop_changes(ret, old_val, prop_value, prop); > + } > + > + if (plane_state->plane->type != DRM_PLANE_TYPE_PRIMARY && > + plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY) { > + drm_dbg_atomic(prop->dev, > + "[OBJECT:%d] Only primary or overlay planes can be changed during async flip\n", > + obj->id); > + return -EINVAL; > + } > + > + return 0; > +} > + > static const struct drm_plane_funcs dm_plane_funcs = { > .update_plane = drm_atomic_helper_update_plane, > .disable_plane = drm_atomic_helper_disable_plane, > @@ -1438,6 +1466,7 @@ static const struct drm_plane_funcs dm_plane_funcs = { > .atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state, > .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state, > .format_mod_supported = amdgpu_dm_plane_format_mod_supported, > + .check_async_props = amdgpu_dm_plane_check_async_props, > }; > > int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, > -- > 2.43.0 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch