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[213.67.3.247]) by smtp.gmail.com with ESMTPSA id be37-20020a056512252500b00513dd355e19sm849131lfb.165.2024.03.19.14.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Mar 2024 14:01:40 -0700 (PDT) Date: Tue, 19 Mar 2024 22:01:39 +0100 From: "Edgar E. Iglesias" To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Richard Henderson , Laurent Vivier , Anton Johansson , Alistair Francis Subject: Re: [PATCH-for-9.1 7/8] target/microblaze: Move MMU helpers to sys_helper.c Message-ID: References: <20240319062855.8025-1-philmd@linaro.org> <20240319062855.8025-8-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240319062855.8025-8-philmd@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::12b; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x12b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Mar 19, 2024 at 07:28:54AM +0100, Philippe Mathieu-Daudé wrote: > MMU helpers are only used during system emulation, > move them to sys_helper.c. Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/microblaze/op_helper.c | 48 ---------------------------------- > target/microblaze/sys_helper.c | 47 +++++++++++++++++++++++++++++++++ > 2 files changed, 47 insertions(+), 48 deletions(-) > > diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c > index f6378030b7..45dbed4aaa 100644 > --- a/target/microblaze/op_helper.c > +++ b/target/microblaze/op_helper.c > @@ -381,51 +381,3 @@ void helper_stackprot(CPUMBState *env, target_ulong addr) > cpu_loop_exit_restore(cs, GETPC()); > } > } > - > -#if !defined(CONFIG_USER_ONLY) > -/* Writes/reads to the MMU's special regs end up here. */ > -uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn) > -{ > - return mmu_read(env, ext, rn); > -} > - > -void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v) > -{ > - mmu_write(env, ext, rn, v); > -} > - > -void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, > - unsigned size, MMUAccessType access_type, > - int mmu_idx, MemTxAttrs attrs, > - MemTxResult response, uintptr_t retaddr) > -{ > - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); > - CPUMBState *env = &cpu->env; > - > - qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx > - " physaddr 0x" HWADDR_FMT_plx " size %d access type %s\n", > - addr, physaddr, size, > - access_type == MMU_INST_FETCH ? "INST_FETCH" : > - (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE")); > - > - if (!(env->msr & MSR_EE)) { > - return; > - } > - > - if (access_type == MMU_INST_FETCH) { > - if (!cpu->cfg.iopb_bus_exception) { > - return; > - } > - env->esr = ESR_EC_INSN_BUS; > - } else { > - if (!cpu->cfg.dopb_bus_exception) { > - return; > - } > - env->esr = ESR_EC_DATA_BUS; > - } > - > - env->ear = addr; > - cs->exception_index = EXCP_HW_EXCP; > - cpu_loop_exit_restore(cs, retaddr); > -} > -#endif > diff --git a/target/microblaze/sys_helper.c b/target/microblaze/sys_helper.c > index 5180500354..7531f95ca7 100644 > --- a/target/microblaze/sys_helper.c > +++ b/target/microblaze/sys_helper.c > @@ -21,6 +21,7 @@ > #include "qemu/osdep.h" > #include "cpu.h" > #include "exec/exec-all.h" > +#include "exec/helper-proto.h" > #include "qemu/host-utils.h" > #include "exec/log.h" > > @@ -292,3 +293,49 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, > cs->exception_index = EXCP_HW_EXCP; > cpu_loop_exit(cs); > } > + > +/* Writes/reads to the MMU's special regs end up here. */ > +uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn) > +{ > + return mmu_read(env, ext, rn); > +} > + > +void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v) > +{ > + mmu_write(env, ext, rn, v); > +} > + > +void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, > + unsigned size, MMUAccessType access_type, > + int mmu_idx, MemTxAttrs attrs, > + MemTxResult response, uintptr_t retaddr) > +{ > + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); > + CPUMBState *env = &cpu->env; > + > + qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx > + " physaddr 0x" HWADDR_FMT_plx " size %d access type %s\n", > + addr, physaddr, size, > + access_type == MMU_INST_FETCH ? "INST_FETCH" : > + (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE")); > + > + if (!(env->msr & MSR_EE)) { > + return; > + } > + > + if (access_type == MMU_INST_FETCH) { > + if (!cpu->cfg.iopb_bus_exception) { > + return; > + } > + env->esr = ESR_EC_INSN_BUS; > + } else { > + if (!cpu->cfg.dopb_bus_exception) { > + return; > + } > + env->esr = ESR_EC_DATA_BUS; > + } > + > + env->ear = addr; > + cs->exception_index = EXCP_HW_EXCP; > + cpu_loop_exit_restore(cs, retaddr); > +} > -- > 2.41.0 >