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[34.140.232.180]) by smtp.gmail.com with ESMTPSA id bs24-20020a056000071800b00341de001396sm311379wrb.110.2024.03.26.12.12.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 12:12:56 -0700 (PDT) Date: Tue, 26 Mar 2024 19:12:53 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: iommu@lists.linux.dev, Joerg Roedel , linux-arm-kernel@lists.infradead.org, Robin Murphy , Will Deacon , Eric Auger , Jean-Philippe Brucker , Moritz Fischer , Michael Shavit , Nicolin Chen , patches@lists.linux.dev, Shameerali Kolothum Thodi Subject: Re: [PATCH v5 05/27] iommu/arm-smmu-v3: Make CD programming use arm_smmu_write_entry() Message-ID: References: <0-v5-9a37e0c884ce+31e3-smmuv3_newapi_p2_jgg@nvidia.com> <5-v5-9a37e0c884ce+31e3-smmuv3_newapi_p2_jgg@nvidia.com> <20240326183055.GL6245@nvidia.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240326183055.GL6245@nvidia.com> On Tue, Mar 26, 2024 at 03:30:55PM -0300, Jason Gunthorpe wrote: > On Sat, Mar 23, 2024 at 01:02:15PM +0000, Mostafa Saleh wrote: > > > +static void arm_smmu_get_cd_used(const __le64 *ent, __le64 *used_bits) > > > +{ > > > + used_bits[0] = cpu_to_le64(CTXDESC_CD_0_V); > > > + if (!(ent[0] & cpu_to_le64(CTXDESC_CD_0_V))) > > > + return; > > > + memset(used_bits, 0xFF, sizeof(struct arm_smmu_cd)); > > > > This is a slightly different approach than what the driver does for STEs, > > where it explicitly sets the used bits. Is there a reason for that? > > It is just more compact this way IMHO, it seems too much to have this mechanism for CDs for just one SVA case, but I'll need to go through the whole seires first to make sure I am not missing anything. > > > + /* EPD0 means T0SZ/TG0/IR0/OR0/SH0/TTB0 are IGNORED */ > > > + if (ent[0] & cpu_to_le64(CTXDESC_CD_0_TCR_EPD0)) { > > > + used_bits[0] &= ~cpu_to_le64( > > > + CTXDESC_CD_0_TCR_T0SZ | CTXDESC_CD_0_TCR_TG0 | > > > + CTXDESC_CD_0_TCR_IRGN0 | CTXDESC_CD_0_TCR_ORGN0 | > > > + CTXDESC_CD_0_TCR_SH0); > > > + used_bits[1] &= ~cpu_to_le64(CTXDESC_CD_1_TTB0_MASK); > > > + } > > > +} > > > > We should add a comment about EPD1 maybe? > > Driver doesn't use TTB1? Yes, it's not immediately obvious why we ignore EPD1, so maybe it's worth a comment to highlight that, but no strong opinion. Thanks, Mostafa From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6D278C54E67 for ; Tue, 26 Mar 2024 19:13:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=W4lkCOG8kLLX/M8hPx4tgplWBbg0fqXr4gCPpUc9QVQ=; b=B5BzAPT/z6enBe M9etDq/doKkneis9zJpLuQKqOHcQ6NrTGpqqCLqNU4DEkWr2ZpEjRuzRa8R06e+Xku/anYS42PcmW tK9ehIpPtch7xl9AtOoDn+J1B4uCMHKRFCyFY7NqU9cvyGmJ9OaefU9d+rgDM7EfI7e+a3wqSWkxO Nh5Leg3EcCz+vKF2aTqUaD+mTNj4KbYBkh0xoEYCrKn9Ffnb0oPrhk8JiBBIpnEfrD/l7ATHxPnWV D5shvcoM2J/thfOp+gtf25JJUhx8mXaP1A0GeTizf/BPYS5k4yLRgZV6PpDJgDv2xnpD9be4HIrdg r5XDxq3QUjKW1+BYXs4w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rpCER-000000066Z0-2GWR; Tue, 26 Mar 2024 19:13:11 +0000 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rpCEO-000000066Td-15aw for linux-arm-kernel@lists.infradead.org; Tue, 26 Mar 2024 19:13:10 +0000 Received: by mail-wm1-x32c.google.com with SMTP id 5b1f17b1804b1-413f8c8192eso19735e9.0 for ; Tue, 26 Mar 2024 12:12:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1711480377; x=1712085177; darn=lists.infradead.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=TdvoN9pLMcneCwvNfRcnO2A70DXtwDqMLrFJIxZqg2E=; b=RC9+pj4zk26MtMrInVkz+dCjg749sv5d6gfITK7gWp5ADXITmyIqBkXVDI1JoSr0ZK 1h+uq4SJDBq90L+Zn6G/CG1ftlvNmdD/BqWhwk57wvoT/L/m41/e1JSncvVtVr/i5dr2 iRxfCVo+bJdMjFq8/6ruU4CP0tTRE1xZ6tkhA5jzfXihUvrki8UM8UsbGGl8P4lVb0T0 d7bqXqsgfYlEoanTADj08EkA+iflzt6feo20NN2ftrh7QslDs+pGvTl0f1KqUN+d947f SAUYNsEoBK8HJb3uhEQG7U0+je6i2O0uHhFpuWRklh+Ec2d4CzQlPo3MQpQuYBFTu9wP FztQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711480377; x=1712085177; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=TdvoN9pLMcneCwvNfRcnO2A70DXtwDqMLrFJIxZqg2E=; b=kHVQh3ZusdoRn31EHqPFXznlhd5dWgsxz8igzug4F54+3qzfTLEweu2797H++R/gv3 vMpdg30M85fbmLc2WtL6HoM7dDk2dQ7oTz03FPTfmA+6dxy92sTHvysvZ30jX4UN2rZ5 ebfgrRVwECVRpXQzUqzJV4U65B8mdSfxYHQXHVNEQXxd+Z0HNP6PggJSiWM3gY7Ve9pW mK/8hkImUIVr/uymrRRVnXRLksifGiQhz5/1waHWTIXo0GBRuhhZp6KXKmsZdLGE4lc2 wUha6wBlnRefwKPtgr6v1BtiA50X1fLJo0rxsskO9ucZKddxDZwHXieQbNTpiGge8FbC rd0g== X-Forwarded-Encrypted: i=1; AJvYcCUHbmMymfkFIIQgW5BZ2Rixh2C2g0hiKgIVrA1WyPRVVWEH0ZF8qVhJKFc4DDj4414OQx1hQhqbkPi7Jx+t0GuOgIzR6LcIR5zKO51vy+xHugaGjzc= X-Gm-Message-State: AOJu0YzVNWUA2LcmiPaGZLZsj4tVbYGmpfRmOkBoZE7K6R0vOAoEoe6o ptxJs0jl+t4KJ8YllrkLwc/XrqEeRJFcJkhAJR4FEIuNMO4BeqAIjGxuN2yvbA== X-Google-Smtp-Source: AGHT+IEbk21x/F4NM5dydbnppbzz05fY51i8qAeXlO7V6M0rwLjEk263RPNp0tgBz6RjvVc+dJQPVA== X-Received: by 2002:a05:600c:a018:b0:414:11:ec14 with SMTP id jg24-20020a05600ca01800b004140011ec14mr29973wmb.6.1711480377299; Tue, 26 Mar 2024 12:12:57 -0700 (PDT) Received: from google.com (180.232.140.34.bc.googleusercontent.com. [34.140.232.180]) by smtp.gmail.com with ESMTPSA id bs24-20020a056000071800b00341de001396sm311379wrb.110.2024.03.26.12.12.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 12:12:56 -0700 (PDT) Date: Tue, 26 Mar 2024 19:12:53 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: iommu@lists.linux.dev, Joerg Roedel , linux-arm-kernel@lists.infradead.org, Robin Murphy , Will Deacon , Eric Auger , Jean-Philippe Brucker , Moritz Fischer , Michael Shavit , Nicolin Chen , patches@lists.linux.dev, Shameerali Kolothum Thodi Subject: Re: [PATCH v5 05/27] iommu/arm-smmu-v3: Make CD programming use arm_smmu_write_entry() Message-ID: References: <0-v5-9a37e0c884ce+31e3-smmuv3_newapi_p2_jgg@nvidia.com> <5-v5-9a37e0c884ce+31e3-smmuv3_newapi_p2_jgg@nvidia.com> <20240326183055.GL6245@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240326183055.GL6245@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240326_121308_357412_6D9E43A8 X-CRM114-Status: GOOD ( 19.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Mar 26, 2024 at 03:30:55PM -0300, Jason Gunthorpe wrote: > On Sat, Mar 23, 2024 at 01:02:15PM +0000, Mostafa Saleh wrote: > > > +static void arm_smmu_get_cd_used(const __le64 *ent, __le64 *used_bits) > > > +{ > > > + used_bits[0] = cpu_to_le64(CTXDESC_CD_0_V); > > > + if (!(ent[0] & cpu_to_le64(CTXDESC_CD_0_V))) > > > + return; > > > + memset(used_bits, 0xFF, sizeof(struct arm_smmu_cd)); > > > > This is a slightly different approach than what the driver does for STEs, > > where it explicitly sets the used bits. Is there a reason for that? > > It is just more compact this way IMHO, it seems too much to have this mechanism for CDs for just one SVA case, but I'll need to go through the whole seires first to make sure I am not missing anything. > > > + /* EPD0 means T0SZ/TG0/IR0/OR0/SH0/TTB0 are IGNORED */ > > > + if (ent[0] & cpu_to_le64(CTXDESC_CD_0_TCR_EPD0)) { > > > + used_bits[0] &= ~cpu_to_le64( > > > + CTXDESC_CD_0_TCR_T0SZ | CTXDESC_CD_0_TCR_TG0 | > > > + CTXDESC_CD_0_TCR_IRGN0 | CTXDESC_CD_0_TCR_ORGN0 | > > > + CTXDESC_CD_0_TCR_SH0); > > > + used_bits[1] &= ~cpu_to_le64(CTXDESC_CD_1_TTB0_MASK); > > > + } > > > +} > > > > We should add a comment about EPD1 maybe? > > Driver doesn't use TTB1? Yes, it's not immediately obvious why we ignore EPD1, so maybe it's worth a comment to highlight that, but no strong opinion. Thanks, Mostafa _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel