All of lore.kernel.org
 help / color / mirror / Atom feed
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: <sai.gowtham.ch@intel.com>
Cc: <igt-dev@lists.freedesktop.org>
Subject: Re: [PATCH i-g-t 2/3] tests/intel/xe_pm: Validate vm-bind prefetch flag with suspend and resume
Date: Thu, 28 Mar 2024 14:05:32 -0400	[thread overview]
Message-ID: <ZgWxbKP9Rxvt1q-7@intel.com> (raw)
In-Reply-To: <20240325201045.25805-3-sai.gowtham.ch@intel.com>

On Tue, Mar 26, 2024 at 01:40:44AM +0530, sai.gowtham.ch@intel.com wrote:
> From: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> 
> Test functionality of vm_bind prefetch with S&R
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch@intel.com>
> ---
>  tests/intel/xe_pm.c | 20 +++++++++++++++++---
>  1 file changed, 17 insertions(+), 3 deletions(-)
> 
> diff --git a/tests/intel/xe_pm.c b/tests/intel/xe_pm.c
> index 8659e87cc..e016f2bca 100644
> --- a/tests/intel/xe_pm.c
> +++ b/tests/intel/xe_pm.c
> @@ -34,6 +34,7 @@
>  #define MAGIC_2 0xdeadbeef
>  
>  #define USERPTR         (0x1 << 0)
> +#define PREFETCH        (0x1 << 5)

why 0x5? we don't need to copy verbatim this from other tests.
0x2 makes more sense here.

>  
>  typedef struct {
>  	int fd_xe;
> @@ -289,6 +290,7 @@ static void close_fw_handle(int sig)
>   * arg[2]:
>   *
>   * @usrptr:     usrptr
> + * @prefetch:  prefetch
>   */
>  static void
>  test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
> @@ -340,9 +342,16 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
>  	if (flags & USERPTR) {
>  		data = aligned_alloc(xe_get_default_alignment(device.fd_xe), bo_size);
>  	} else {
> -		bo = xe_bo_create(device.fd_xe, vm, bo_size,
> -				  vram_if_possible(device.fd_xe, eci->gt_id),
> -				  DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> +
> +		if (flags & PREFETCH)
> +			bo = xe_bo_create(device.fd_xe, 0, bo_size,
> +					  all_memory_regions(device.fd_xe) |
> +					  vram_if_possible(device.fd_xe, 0),
> +					  DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);
> +		else
> +			bo = xe_bo_create(device.fd_xe, vm, bo_size,
> +					  vram_if_possible(device.fd_xe, eci->gt_id),
> +					  DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM);

why? I don't see this in other tests with 'prefetch'?

>  		data = xe_bo_map(device.fd_xe, bo, bo_size);
>  	}
>  	memset(data, 0, bo_size);
> @@ -362,6 +371,10 @@ test_exec(device_t device, struct drm_xe_engine_class_instance *eci,
>  		xe_vm_bind_userptr_async(device.fd_xe, vm, bind_exec_queues[0],
>  					 to_user_pointer(data), addr, bo_size, sync, 1);
>  
> +	if (flags & PREFETCH)
> +		xe_vm_prefetch_async(device.fd_xe, vm, bind_exec_queues[0], 0, addr,
> +				     bo_size, sync, 1, 0);
> +
>  	if (check_rpm && runtime_usage_available(device.pci_xe))
>  		igt_assert(igt_pm_get_runtime_usage(device.pci_xe) > rpm_usage);
>  
> @@ -615,6 +628,7 @@ igt_main
>  		unsigned int flags;
>  	} vm_op[] = {
>  		{ "usrptr", USERPTR },
> +		{ "prefetch", PREFETCH },
>  		{ NULL },
>  	};
>  
> -- 
> 2.39.1
> 

  reply	other threads:[~2024-03-28 18:05 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-25 20:10 [PATCH i-g-t 0/3] tests/intel/xe_pm: Tests to validate vm-bind sai.gowtham.ch
2024-03-25 20:10 ` [PATCH i-g-t 1/3] tests/intel/xe_pm: Test validates vm-bind userptr flag with suspend and resume sai.gowtham.ch
2024-03-28 18:00   ` Rodrigo Vivi
2024-03-25 20:10 ` [PATCH i-g-t 2/3] tests/intel/xe_pm: Validate vm-bind prefetch " sai.gowtham.ch
2024-03-28 18:05   ` Rodrigo Vivi [this message]
2024-03-25 20:10 ` [PATCH i-g-t 3/3] tests/intel/xe_pm: Tests vm-unbind all flag functionality with s&R sai.gowtham.ch
2024-03-28 18:16   ` Rodrigo Vivi
2024-03-25 22:00 ` ✓ CI.xeBAT: success for tests/intel/xe_pm: Tests to validate vm-bind (rev2) Patchwork
2024-03-25 22:08 ` ✓ Fi.CI.BAT: " Patchwork
2024-03-26  4:39 ` ✗ Fi.CI.IGT: failure " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2024-04-01 18:46 [PATCH i-g-t 0/3] tests/intel/xe_pm: Tests to validate vm-bind with S&R sai.gowtham.ch
2024-04-01 18:46 ` [PATCH i-g-t 2/3] tests/intel/xe_pm: Validate vm-bind prefetch flag with suspend and resume sai.gowtham.ch
2024-04-03 20:27   ` Rodrigo Vivi
2024-04-15  8:40 [PATCH i-g-t 0/3] tests/intel/xe_pm: Tests to validate vm-bind with S&R sai.gowtham.ch
2024-04-15  8:40 ` [PATCH i-g-t 2/3] tests/intel/xe_pm: Validate vm-bind prefetch flag with suspend and resume sai.gowtham.ch
2024-04-16  1:29   ` Rodrigo Vivi
2024-04-16 20:58     ` Rodrigo Vivi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ZgWxbKP9Rxvt1q-7@intel.com \
    --to=rodrigo.vivi@intel.com \
    --cc=igt-dev@lists.freedesktop.org \
    --cc=sai.gowtham.ch@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.