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AJvYcCVCIraXTqg9vySkIJDB0RCsmlNLyxM26F/LZRejSmPlaoFcVMXQtcW4UaNKqH+jpxv6xN17dmubz4epZK2iRsztWGawmoc= X-Gm-Message-State: AOJu0Yw1EhwJdUkDU/ep84XfYguy8X7LyhvYWyYF3P0PDFiPuYIKxhl1 1EwgGAVl9Cm38/ZACLIP64lxLPKZ2ZUzyPW05/gg5mIys/btILafupO6m8f3T8guW3mH06L2dk/ iIw== X-Google-Smtp-Source: AGHT+IGLwF+HfzZtGn8zwa1qm1dvlv2UkAX6QqEas4f4AXsrP0etNn5dV5dMejYckrKUvPHWx3YS/a/UIOw= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a17:902:db08:b0:1e5:10e5:344 with SMTP id m8-20020a170902db0800b001e510e50344mr8380plx.3.1712932051773; Fri, 12 Apr 2024 07:27:31 -0700 (PDT) Date: Fri, 12 Apr 2024 07:27:30 -0700 In-Reply-To: Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240405223110.1609888-1-jacob.jun.pan@linux.intel.com> <20240405223110.1609888-6-jacob.jun.pan@linux.intel.com> Message-ID: Subject: Re: [PATCH v2 05/13] x86/irq: Reserve a per CPU IDT vector for posted MSIs From: Sean Christopherson To: Kevin Tian Cc: Jacob Pan , LKML , X86 Kernel , Peter Zijlstra , "iommu@lists.linux.dev" , Thomas Gleixner , Lu Baolu , "kvm@vger.kernel.org" , Dave Hansen , Joerg Roedel , Peter Anvin , Borislav Petkov , Ingo Molnar , Paul E Luse , Dan Williams , Jens Axboe , Ashok Raj , "maz@kernel.org" , Robin Murphy , "jim.harris@samsung.com" , "a.manzanares@samsung.com" , Bjorn Helgaas , Guang Zeng , "robert.hoo.linux@gmail.com" Content-Type: text/plain; charset="us-ascii" On Fri, Apr 12, 2024, Kevin Tian wrote: > > From: Jacob Pan > > Sent: Saturday, April 6, 2024 6:31 AM > > > > +/* > > + * Posted interrupt notification vector for all device MSIs delivered to > > + * the host kernel. > > + */ > > +#define POSTED_MSI_NOTIFICATION_VECTOR 0xeb > > #define NR_VECTORS 256 > > > > Every interrupt is kind of a notification. FWIW, I find value in having "notification" in the name to differentiate between the IRQ that is notifying the CPU that there's a posted IRQ to be processed, and the posted IRQ itself.