From mboxrd@z Thu Jan 1 00:00:00 1970 From: Deepak Gupta Date: Sat, 27 Apr 2024 08:36:04 -0700 Subject: [RFC PATCH 6/7] riscv: kvm: add SBI FWFT support for SBI_FWFT_DOUBLE_TRAP_ENABLE In-Reply-To: References: <20240418142701.1493091-1-cleger@rivosinc.com> <20240418142701.1493091-7-cleger@rivosinc.com> Message-ID: List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On Fri, Apr 26, 2024 at 06:17:08PM -0700, Deepak Gupta wrote: >On Thu, Apr 18, 2024 at 04:26:45PM +0200, Cl?ment L?ger wrote: >>Add support in KVM SBI FWFT extension to allow VS-mode to request double >>trap enabling. Double traps can then be generated by VS-mode, allowing >>M-mode to redirect them to S-mode. >> >>Signed-off-by: Cl?ment L?ger >>--- >>arch/riscv/include/asm/csr.h | 1 + >>arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h | 2 +- >>arch/riscv/kvm/vcpu_sbi_fwft.c | 41 ++++++++++++++++++++++ >>3 files changed, 43 insertions(+), 1 deletion(-) >> >>diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h >>index 905cdf894a57..ee1b73655bec 100644 >>--- a/arch/riscv/include/asm/csr.h >>+++ b/arch/riscv/include/asm/csr.h >>@@ -196,6 +196,7 @@ >>/* xENVCFG flags */ >>#define ENVCFG_STCE (_AC(1, ULL) << 63) >>#define ENVCFG_PBMTE (_AC(1, ULL) << 62) >>+#define ENVCFG_DTE (_AC(1, ULL) << 59) >>#define ENVCFG_CBZE (_AC(1, UL) << 7) >>#define ENVCFG_CBCFE (_AC(1, UL) << 6) >>#define ENVCFG_CBIE_SHIFT 4 >>diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h b/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h >>index 7dc1b80c7e6c..a9e20d655126 100644 >>--- a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h >>+++ b/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h >>@@ -11,7 +11,7 @@ >> >>#include >> >>-#define KVM_SBI_FWFT_FEATURE_COUNT 1 >>+#define KVM_SBI_FWFT_FEATURE_COUNT 2 >> >>struct kvm_sbi_fwft_config; >>struct kvm_vcpu; >>diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c >>index b9b7f8fa6d22..9e8e397eb02f 100644 >>--- a/arch/riscv/kvm/vcpu_sbi_fwft.c >>+++ b/arch/riscv/kvm/vcpu_sbi_fwft.c >>@@ -9,10 +9,19 @@ >>#include >>#include >>#include >>+#include >>#include >>#include >>#include >> >>+#ifdef CONFIG_32BIT >>+# define CSR_HENVCFG_DBLTRP CSR_HENVCFGH >>+# define DBLTRP_DTE (ENVCFG_DTE >> 32) >>+#else >>+# define CSR_HENVCFG_DBLTRP CSR_HENVCFG >>+# define DBLTRP_DTE ENVCFG_DTE >>+#endif >>+ >>#define MIS_DELEG (1UL << EXC_LOAD_MISALIGNED | 1UL << EXC_STORE_MISALIGNED) >> >>static int kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu, >>@@ -36,6 +45,33 @@ static int kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu, >> return SBI_SUCCESS; >>} >> >>+static int kvm_sbi_fwft_set_double_trap(struct kvm_vcpu *vcpu, >>+ struct kvm_sbi_fwft_config *conf, >>+ unsigned long value) >>+{ >>+ if (!riscv_double_trap_enabled()) >>+ return SBI_ERR_NOT_SUPPORTED; > >Why its required to check whether host has enabled double trap for itself ? >It's orthogonal to guest asking hypervisor to enable double trap. > >Probably you need a check here whether underlying FW supports handling double >trap. > >Am I missing something here? > On this I am indeed missing that menvcfg.DTE has to be 1 for any less priv. So, nevermind on this comment. Sorry about that. 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Sat, 27 Apr 2024 08:36:06 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id r6-20020a17090a5c8600b002ade3490b4asm10494669pji.22.2024.04.27.08.36.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Apr 2024 08:36:06 -0700 (PDT) Date: Sat, 27 Apr 2024 08:36:04 -0700 From: Deepak Gupta To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Ved Shanbhogue Subject: Re: [RFC PATCH 6/7] riscv: kvm: add SBI FWFT support for SBI_FWFT_DOUBLE_TRAP_ENABLE Message-ID: References: <20240418142701.1493091-1-cleger@rivosinc.com> <20240418142701.1493091-7-cleger@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240427_083611_873020_B0CCD73E X-CRM114-Status: GOOD ( 11.72 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, Apr 26, 2024 at 06:17:08PM -0700, Deepak Gupta wrote: >On Thu, Apr 18, 2024 at 04:26:45PM +0200, Cl=E9ment L=E9ger wrote: >>Add support in KVM SBI FWFT extension to allow VS-mode to request double >>trap enabling. Double traps can then be generated by VS-mode, allowing >>M-mode to redirect them to S-mode. >> >>Signed-off-by: Cl=E9ment L=E9ger >>--- >>arch/riscv/include/asm/csr.h | 1 + >>arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h | 2 +- >>arch/riscv/kvm/vcpu_sbi_fwft.c | 41 ++++++++++++++++++++++ >>3 files changed, 43 insertions(+), 1 deletion(-) >> >>diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h >>index 905cdf894a57..ee1b73655bec 100644 >>--- a/arch/riscv/include/asm/csr.h >>+++ b/arch/riscv/include/asm/csr.h >>@@ -196,6 +196,7 @@ >>/* xENVCFG flags */ >>#define ENVCFG_STCE (_AC(1, ULL) << 63) >>#define ENVCFG_PBMTE (_AC(1, ULL) << 62) >>+#define ENVCFG_DTE (_AC(1, ULL) << 59) >>#define ENVCFG_CBZE (_AC(1, UL) << 7) >>#define ENVCFG_CBCFE (_AC(1, UL) << 6) >>#define ENVCFG_CBIE_SHIFT 4 >>diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h b/arch/riscv/incl= ude/asm/kvm_vcpu_sbi_fwft.h >>index 7dc1b80c7e6c..a9e20d655126 100644 >>--- a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h >>+++ b/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h >>@@ -11,7 +11,7 @@ >> >>#include >> >>-#define KVM_SBI_FWFT_FEATURE_COUNT 1 >>+#define KVM_SBI_FWFT_FEATURE_COUNT 2 >> >>struct kvm_sbi_fwft_config; >>struct kvm_vcpu; >>diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwf= t.c >>index b9b7f8fa6d22..9e8e397eb02f 100644 >>--- a/arch/riscv/kvm/vcpu_sbi_fwft.c >>+++ b/arch/riscv/kvm/vcpu_sbi_fwft.c >>@@ -9,10 +9,19 @@ >>#include >>#include >>#include >>+#include >>#include >>#include >>#include >> >>+#ifdef CONFIG_32BIT >>+# define CSR_HENVCFG_DBLTRP CSR_HENVCFGH >>+# define DBLTRP_DTE (ENVCFG_DTE >> 32) >>+#else >>+# define CSR_HENVCFG_DBLTRP CSR_HENVCFG >>+# define DBLTRP_DTE ENVCFG_DTE >>+#endif >>+ >>#define MIS_DELEG (1UL << EXC_LOAD_MISALIGNED | 1UL << EXC_STORE_MISALIGN= ED) >> >>static int kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu, >>@@ -36,6 +45,33 @@ static int kvm_sbi_fwft_get_misaligned_delegation(stru= ct kvm_vcpu *vcpu, >> return SBI_SUCCESS; >>} >> >>+static int kvm_sbi_fwft_set_double_trap(struct kvm_vcpu *vcpu, >>+ struct kvm_sbi_fwft_config *conf, >>+ unsigned long value) >>+{ >>+ if (!riscv_double_trap_enabled()) >>+ return SBI_ERR_NOT_SUPPORTED; > >Why its required to check whether host has enabled double trap for itself ? >It's orthogonal to guest asking hypervisor to enable double trap. > >Probably you need a check here whether underlying FW supports handling dou= ble >trap. > >Am I missing something here? > On this I am indeed missing that menvcfg.DTE has to be 1 for any less priv. So, nevermind on this comment. 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Sat, 27 Apr 2024 08:36:06 -0700 (PDT) Date: Sat, 27 Apr 2024 08:36:04 -0700 From: Deepak Gupta To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Ved Shanbhogue Subject: Re: [RFC PATCH 6/7] riscv: kvm: add SBI FWFT support for SBI_FWFT_DOUBLE_TRAP_ENABLE Message-ID: References: <20240418142701.1493091-1-cleger@rivosinc.com> <20240418142701.1493091-7-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Fri, Apr 26, 2024 at 06:17:08PM -0700, Deepak Gupta wrote: >On Thu, Apr 18, 2024 at 04:26:45PM +0200, Clément Léger wrote: >>Add support in KVM SBI FWFT extension to allow VS-mode to request double >>trap enabling. Double traps can then be generated by VS-mode, allowing >>M-mode to redirect them to S-mode. >> >>Signed-off-by: Clément Léger >>--- >>arch/riscv/include/asm/csr.h | 1 + >>arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h | 2 +- >>arch/riscv/kvm/vcpu_sbi_fwft.c | 41 ++++++++++++++++++++++ >>3 files changed, 43 insertions(+), 1 deletion(-) >> >>diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h >>index 905cdf894a57..ee1b73655bec 100644 >>--- a/arch/riscv/include/asm/csr.h >>+++ b/arch/riscv/include/asm/csr.h >>@@ -196,6 +196,7 @@ >>/* xENVCFG flags */ >>#define ENVCFG_STCE (_AC(1, ULL) << 63) >>#define ENVCFG_PBMTE (_AC(1, ULL) << 62) >>+#define ENVCFG_DTE (_AC(1, ULL) << 59) >>#define ENVCFG_CBZE (_AC(1, UL) << 7) >>#define ENVCFG_CBCFE (_AC(1, UL) << 6) >>#define ENVCFG_CBIE_SHIFT 4 >>diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h b/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h >>index 7dc1b80c7e6c..a9e20d655126 100644 >>--- a/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h >>+++ b/arch/riscv/include/asm/kvm_vcpu_sbi_fwft.h >>@@ -11,7 +11,7 @@ >> >>#include >> >>-#define KVM_SBI_FWFT_FEATURE_COUNT 1 >>+#define KVM_SBI_FWFT_FEATURE_COUNT 2 >> >>struct kvm_sbi_fwft_config; >>struct kvm_vcpu; >>diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c >>index b9b7f8fa6d22..9e8e397eb02f 100644 >>--- a/arch/riscv/kvm/vcpu_sbi_fwft.c >>+++ b/arch/riscv/kvm/vcpu_sbi_fwft.c >>@@ -9,10 +9,19 @@ >>#include >>#include >>#include >>+#include >>#include >>#include >>#include >> >>+#ifdef CONFIG_32BIT >>+# define CSR_HENVCFG_DBLTRP CSR_HENVCFGH >>+# define DBLTRP_DTE (ENVCFG_DTE >> 32) >>+#else >>+# define CSR_HENVCFG_DBLTRP CSR_HENVCFG >>+# define DBLTRP_DTE ENVCFG_DTE >>+#endif >>+ >>#define MIS_DELEG (1UL << EXC_LOAD_MISALIGNED | 1UL << EXC_STORE_MISALIGNED) >> >>static int kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu, >>@@ -36,6 +45,33 @@ static int kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu, >> return SBI_SUCCESS; >>} >> >>+static int kvm_sbi_fwft_set_double_trap(struct kvm_vcpu *vcpu, >>+ struct kvm_sbi_fwft_config *conf, >>+ unsigned long value) >>+{ >>+ if (!riscv_double_trap_enabled()) >>+ return SBI_ERR_NOT_SUPPORTED; > >Why its required to check whether host has enabled double trap for itself ? >It's orthogonal to guest asking hypervisor to enable double trap. > >Probably you need a check here whether underlying FW supports handling double >trap. > >Am I missing something here? > On this I am indeed missing that menvcfg.DTE has to be 1 for any less priv. So, nevermind on this comment. Sorry about that.