From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Serge Semin <fancer.lancer@gmail.com>
Cc: "Viresh Kumar" <vireshk@kernel.org>,
"Vinod Koul" <vkoul@kernel.org>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Jiri Slaby" <jirislaby@kernel.org>,
dmaengine@vger.kernel.org, linux-serial@vger.kernel.org,
linux-kernel@vger.kernel.org,
"Viresh Kumar" <viresh.kumar@linaro.org>
Subject: Re: [PATCH 2/4] dmaengine: dw: Add memory bus width verification
Date: Thu, 18 Apr 2024 12:37:09 +0300 [thread overview]
Message-ID: <ZiDpxb-diEt91My4@smile.fi.intel.com> (raw)
In-Reply-To: <nroj7c7hvo5ao5gfuububc2zqj7z4rpkoji5flhbrie3xrmgwg@6rhzllxwgj4w>
On Wed, Apr 17, 2024 at 09:52:42PM +0300, Serge Semin wrote:
> On Wed, Apr 17, 2024 at 08:28:06PM +0300, Andy Shevchenko wrote:
> > On Wed, Apr 17, 2024 at 08:13:59PM +0300, Serge Semin wrote:
...
> > Got it. Maybe a little summary in the code to explain all this magic?
>
> Will it be enough to add something like this:
> /*
> * It's possible to have a data portion locked in the DMA FIFO in case
> * of the channel suspension. Subsequent channel disabling will cause
> * that data silent loss. In order to prevent that maintain the src
> * and dst transfer widths coherency by means of the relation:
> * (CTLx.SRC_TR_WIDTH * CTLx.SRC_MSIZE >= CTLx.DST_TR_WIDTH)
> */
Yes, and you may add something like
"Look for the details in the commit message that brings this change."
at the end of it.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2024-04-18 9:37 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-16 16:28 [PATCH 0/4] dmaengine: dw: Fix src/dst addr width misconfig Serge Semin
2024-04-16 16:28 ` [PATCH 1/4] dmaengine: dw: Add peripheral bus width verification Serge Semin
2024-04-16 18:00 ` Andy Shevchenko
2024-04-17 19:54 ` Serge Semin
2024-04-18 9:43 ` Andy Shevchenko
2024-04-18 15:47 ` Serge Semin
2024-04-16 16:28 ` [PATCH 2/4] dmaengine: dw: Add memory " Serge Semin
2024-04-16 18:47 ` Andy Shevchenko
2024-04-17 17:13 ` Serge Semin
2024-04-17 17:28 ` Andy Shevchenko
2024-04-17 18:52 ` Serge Semin
2024-04-18 9:37 ` Andy Shevchenko [this message]
2024-04-18 15:52 ` Serge Semin
2024-04-16 16:28 ` [PATCH 3/4] dmaengine: dw: Simplify prepare CTL_LO methods Serge Semin
2024-04-16 19:04 ` Andy Shevchenko
2024-04-17 20:11 ` Serge Semin
2024-04-18 11:47 ` Andy Shevchenko
2024-04-18 19:00 ` Serge Semin
2024-04-18 21:00 ` Andy Shevchenko
2024-04-19 9:19 ` Serge Semin
2024-04-16 16:28 ` [PATCH 4/4] dmaengine: dw: Simplify max-burst calculation procedure Serge Semin
2024-04-16 19:11 ` Andy Shevchenko
2024-04-17 20:35 ` Serge Semin
2024-04-18 11:49 ` Andy Shevchenko
2024-04-18 19:10 ` Serge Semin
2024-04-16 19:13 ` [PATCH 0/4] dmaengine: dw: Fix src/dst addr width misconfig Andy Shevchenko
2024-04-17 17:34 ` Serge Semin
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