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[34.140.232.180]) by smtp.gmail.com with ESMTPSA id h15-20020a05600c350f00b00418d68df226sm8516063wmq.0.2024.04.19.14.02.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Apr 2024 14:02:36 -0700 (PDT) Date: Fri, 19 Apr 2024 21:02:32 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: iommu@lists.linux.dev, Joerg Roedel , linux-arm-kernel@lists.infradead.org, Robin Murphy , Will Deacon , Eric Auger , Moritz Fischer , Moritz Fischer , Michael Shavit , Nicolin Chen , patches@lists.linux.dev, Shameerali Kolothum Thodi Subject: Re: [PATCH v7 1/9] iommu/arm-smmu-v3: Add an ops indirection to the STE code Message-ID: References: <0-v7-cb149db3a320+3b5-smmuv3_newapi_p2_jgg@nvidia.com> <1-v7-cb149db3a320+3b5-smmuv3_newapi_p2_jgg@nvidia.com> Precedence: bulk X-Mailing-List: iommu@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1-v7-cb149db3a320+3b5-smmuv3_newapi_p2_jgg@nvidia.com> Hi Jason, On Tue, Apr 16, 2024 at 04:28:12PM -0300, Jason Gunthorpe wrote: > Prepare to put the CD code into the same mechanism. Add an ops indirection > around all the STE specific code and make the worker functions independent > of the entry content being processed. > > get_used and sync ops are provided to hook the correct code. > > Signed-off-by: Michael Shavit > Reviewed-by: Michael Shavit > Tested-by: Nicolin Chen > Tested-by: Shameer Kolothum > Signed-off-by: Jason Gunthorpe > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 178 ++++++++++++-------- > 1 file changed, 106 insertions(+), 72 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 79c18e95dd293e..bf105e914d38b1 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -42,8 +42,20 @@ enum arm_smmu_msi_index { > ARM_SMMU_MAX_MSIS, > }; > > -static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, > - ioasid_t sid); > +struct arm_smmu_entry_writer_ops; > +struct arm_smmu_entry_writer { > + const struct arm_smmu_entry_writer_ops *ops; > + struct arm_smmu_master *master; > +}; > + > +struct arm_smmu_entry_writer_ops { > + __le64 v_bit; > + void (*get_used)(const __le64 *entry, __le64 *used); > + void (*sync)(struct arm_smmu_entry_writer *writer); > +}; > + > +#define NUM_ENTRY_QWORDS 8 > +static_assert(sizeof(struct arm_smmu_ste) == NUM_ENTRY_QWORDS * sizeof(u64)); > > static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = { > [EVTQ_MSI_INDEX] = { > @@ -972,43 +984,42 @@ void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid) > * would be nice if this was complete according to the spec, but minimally it > * has to capture the bits this driver uses. > */ > -static void arm_smmu_get_ste_used(const struct arm_smmu_ste *ent, > - struct arm_smmu_ste *used_bits) > +static void arm_smmu_get_ste_used(const __le64 *ent, __le64 *used_bits) > { > - unsigned int cfg = FIELD_GET(STRTAB_STE_0_CFG, le64_to_cpu(ent->data[0])); > + unsigned int cfg = FIELD_GET(STRTAB_STE_0_CFG, le64_to_cpu(ent[0])); > > - used_bits->data[0] = cpu_to_le64(STRTAB_STE_0_V); > - if (!(ent->data[0] & cpu_to_le64(STRTAB_STE_0_V))) > + used_bits[0] = cpu_to_le64(STRTAB_STE_0_V); > + if (!(ent[0] & cpu_to_le64(STRTAB_STE_0_V))) > return; > > - used_bits->data[0] |= cpu_to_le64(STRTAB_STE_0_CFG); > + used_bits[0] |= cpu_to_le64(STRTAB_STE_0_CFG); > > /* S1 translates */ > if (cfg & BIT(0)) { > - used_bits->data[0] |= cpu_to_le64(STRTAB_STE_0_S1FMT | > - STRTAB_STE_0_S1CTXPTR_MASK | > - STRTAB_STE_0_S1CDMAX); > - used_bits->data[1] |= > + used_bits[0] |= cpu_to_le64(STRTAB_STE_0_S1FMT | > + STRTAB_STE_0_S1CTXPTR_MASK | > + STRTAB_STE_0_S1CDMAX); > + used_bits[1] |= > cpu_to_le64(STRTAB_STE_1_S1DSS | STRTAB_STE_1_S1CIR | > STRTAB_STE_1_S1COR | STRTAB_STE_1_S1CSH | > STRTAB_STE_1_S1STALLD | STRTAB_STE_1_STRW | > STRTAB_STE_1_EATS); > - used_bits->data[2] |= cpu_to_le64(STRTAB_STE_2_S2VMID); > + used_bits[2] |= cpu_to_le64(STRTAB_STE_2_S2VMID); > } > > /* S2 translates */ > if (cfg & BIT(1)) { > - used_bits->data[1] |= > + used_bits[1] |= > cpu_to_le64(STRTAB_STE_1_EATS | STRTAB_STE_1_SHCFG); > - used_bits->data[2] |= > + used_bits[2] |= > cpu_to_le64(STRTAB_STE_2_S2VMID | STRTAB_STE_2_VTCR | > STRTAB_STE_2_S2AA64 | STRTAB_STE_2_S2ENDI | > STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2R); > - used_bits->data[3] |= cpu_to_le64(STRTAB_STE_3_S2TTB_MASK); > + used_bits[3] |= cpu_to_le64(STRTAB_STE_3_S2TTB_MASK); > } > > if (cfg == STRTAB_STE_0_CFG_BYPASS) > - used_bits->data[1] |= cpu_to_le64(STRTAB_STE_1_SHCFG); > + used_bits[1] |= cpu_to_le64(STRTAB_STE_1_SHCFG); > } > > /* > @@ -1017,57 +1028,55 @@ static void arm_smmu_get_ste_used(const struct arm_smmu_ste *ent, > * unused_update is an intermediate value of entry that has unused bits set to > * their new values. > */ > -static u8 arm_smmu_entry_qword_diff(const struct arm_smmu_ste *entry, > - const struct arm_smmu_ste *target, > - struct arm_smmu_ste *unused_update) > +static u8 arm_smmu_entry_qword_diff(struct arm_smmu_entry_writer *writer, > + const __le64 *entry, const __le64 *target, > + __le64 *unused_update) > { > - struct arm_smmu_ste target_used = {}; > - struct arm_smmu_ste cur_used = {}; > + __le64 target_used[NUM_ENTRY_QWORDS] = {}; > + __le64 cur_used[NUM_ENTRY_QWORDS] = {}; > u8 used_qword_diff = 0; > unsigned int i; > > - arm_smmu_get_ste_used(entry, &cur_used); > - arm_smmu_get_ste_used(target, &target_used); > + writer->ops->get_used(entry, cur_used); > + writer->ops->get_used(target, target_used); > > - for (i = 0; i != ARRAY_SIZE(target_used.data); i++) { > + for (i = 0; i != NUM_ENTRY_QWORDS; i++) { > /* > * Check that masks are up to date, the make functions are not > * allowed to set a bit to 1 if the used function doesn't say it > * is used. > */ > - WARN_ON_ONCE(target->data[i] & ~target_used.data[i]); > + WARN_ON_ONCE(target[i] & ~target_used[i]); > > /* Bits can change because they are not currently being used */ > - unused_update->data[i] = (entry->data[i] & cur_used.data[i]) | > - (target->data[i] & ~cur_used.data[i]); > + unused_update[i] = (entry[i] & cur_used[i]) | > + (target[i] & ~cur_used[i]); > /* > * Each bit indicates that a used bit in a qword needs to be > * changed after unused_update is applied. > */ > - if ((unused_update->data[i] & target_used.data[i]) != > - target->data[i]) > + if ((unused_update[i] & target_used[i]) != target[i]) > used_qword_diff |= 1 << i; > } > return used_qword_diff; > } > > -static bool entry_set(struct arm_smmu_device *smmu, ioasid_t sid, > - struct arm_smmu_ste *entry, > - const struct arm_smmu_ste *target, unsigned int start, > +static bool entry_set(struct arm_smmu_entry_writer *writer, __le64 *entry, > + const __le64 *target, unsigned int start, > unsigned int len) > { > bool changed = false; > unsigned int i; > > for (i = start; len != 0; len--, i++) { > - if (entry->data[i] != target->data[i]) { > - WRITE_ONCE(entry->data[i], target->data[i]); > + if (entry[i] != target[i]) { > + WRITE_ONCE(entry[i], target[i]); > changed = true; > } > } > > if (changed) > - arm_smmu_sync_ste_for_sid(smmu, sid); > + writer->ops->sync(writer); > return changed; > } > > @@ -1097,24 +1106,21 @@ static bool entry_set(struct arm_smmu_device *smmu, ioasid_t sid, > * V=0 process. This relies on the IGNORED behavior described in the > * specification. > */ > -static void arm_smmu_write_ste(struct arm_smmu_master *master, u32 sid, > - struct arm_smmu_ste *entry, > - const struct arm_smmu_ste *target) > +static void arm_smmu_write_entry(struct arm_smmu_entry_writer *writer, > + __le64 *entry, const __le64 *target) > { > - unsigned int num_entry_qwords = ARRAY_SIZE(target->data); > - struct arm_smmu_device *smmu = master->smmu; > - struct arm_smmu_ste unused_update; > + __le64 unused_update[NUM_ENTRY_QWORDS]; > u8 used_qword_diff; > > used_qword_diff = > - arm_smmu_entry_qword_diff(entry, target, &unused_update); > + arm_smmu_entry_qword_diff(writer, entry, target, unused_update); > if (hweight8(used_qword_diff) == 1) { > /* > * Only one qword needs its used bits to be changed. This is a > - * hitless update, update all bits the current STE is ignoring > - * to their new values, then update a single "critical qword" to > - * change the STE and finally 0 out any bits that are now unused > - * in the target configuration. > + * hitless update, update all bits the current STE/CD is > + * ignoring to their new values, then update a single "critical > + * qword" to change the STE/CD and finally 0 out any bits that > + * are now unused in the target configuration. > */ > unsigned int critical_qword_index = ffs(used_qword_diff) - 1; > > @@ -1123,22 +1129,21 @@ static void arm_smmu_write_ste(struct arm_smmu_master *master, u32 sid, > * writing it in the next step anyways. This can save a sync > * when the only change is in that qword. > */ > - unused_update.data[critical_qword_index] = > - entry->data[critical_qword_index]; > - entry_set(smmu, sid, entry, &unused_update, 0, num_entry_qwords); > - entry_set(smmu, sid, entry, target, critical_qword_index, 1); > - entry_set(smmu, sid, entry, target, 0, num_entry_qwords); > + unused_update[critical_qword_index] = > + entry[critical_qword_index]; > + entry_set(writer, entry, unused_update, 0, NUM_ENTRY_QWORDS); > + entry_set(writer, entry, target, critical_qword_index, 1); > + entry_set(writer, entry, target, 0, NUM_ENTRY_QWORDS); > } else if (used_qword_diff) { > /* > * At least two qwords need their inuse bits to be changed. This > * requires a breaking update, zero the V bit, write all qwords > * but 0, then set qword 0 > */ > - unused_update.data[0] = entry->data[0] & > - cpu_to_le64(~STRTAB_STE_0_V); > - entry_set(smmu, sid, entry, &unused_update, 0, 1); > - entry_set(smmu, sid, entry, target, 1, num_entry_qwords - 1); > - entry_set(smmu, sid, entry, target, 0, 1); > + unused_update[0] = entry[0] & (~writer->ops->v_bit); arm_smmu_write_entry() assumes that v_bit is in entry[0] and that “1” means valid (which is true for both STE and CD) so why do we care about it, if we break the STE/CD anyway, why not just do: unused_update[0] = 0; entry_set(writer, entry, unused_update, 0, 1); entry_set(writer, entry, target, 1, NUM_ENTRY_QWORDS - 1) entry_set(writer, entry, target, 0, 1); That makes the code simpler by avoiding having the v_bit in arm_smmu_entry_writer_ops. Thanks, Mostafa > + entry_set(writer, entry, unused_update, 0, 1); > + entry_set(writer, entry, target, 1, NUM_ENTRY_QWORDS - 1); > + entry_set(writer, entry, target, 0, 1); > } else { > /* > * No inuse bit changed. Sanity check that all unused bits are 0 > @@ -1146,18 +1151,7 @@ static void arm_smmu_write_ste(struct arm_smmu_master *master, u32 sid, > * compute_qword_diff(). > */ > WARN_ON_ONCE( > - entry_set(smmu, sid, entry, target, 0, num_entry_qwords)); > - } > - > - /* It's likely that we'll want to use the new STE soon */ > - if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH)) { > - struct arm_smmu_cmdq_ent > - prefetch_cmd = { .opcode = CMDQ_OP_PREFETCH_CFG, > - .prefetch = { > - .sid = sid, > - } }; > - > - arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd); > + entry_set(writer, entry, target, 0, NUM_ENTRY_QWORDS)); > } > } > > @@ -1430,17 +1424,57 @@ arm_smmu_write_strtab_l1_desc(__le64 *dst, struct arm_smmu_strtab_l1_desc *desc) > WRITE_ONCE(*dst, cpu_to_le64(val)); > } > > -static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) > +struct arm_smmu_ste_writer { > + struct arm_smmu_entry_writer writer; > + u32 sid; > +}; > + > +static void arm_smmu_ste_writer_sync_entry(struct arm_smmu_entry_writer *writer) > { > + struct arm_smmu_ste_writer *ste_writer = > + container_of(writer, struct arm_smmu_ste_writer, writer); > struct arm_smmu_cmdq_ent cmd = { > .opcode = CMDQ_OP_CFGI_STE, > .cfgi = { > - .sid = sid, > + .sid = ste_writer->sid, > .leaf = true, > }, > }; > > - arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); > + arm_smmu_cmdq_issue_cmd_with_sync(writer->master->smmu, &cmd); > +} > + > +static const struct arm_smmu_entry_writer_ops arm_smmu_ste_writer_ops = { > + .sync = arm_smmu_ste_writer_sync_entry, > + .get_used = arm_smmu_get_ste_used, > + .v_bit = cpu_to_le64(STRTAB_STE_0_V), > +}; > + > +static void arm_smmu_write_ste(struct arm_smmu_master *master, u32 sid, > + struct arm_smmu_ste *ste, > + const struct arm_smmu_ste *target) > +{ > + struct arm_smmu_device *smmu = master->smmu; > + struct arm_smmu_ste_writer ste_writer = { > + .writer = { > + .ops = &arm_smmu_ste_writer_ops, > + .master = master, > + }, > + .sid = sid, > + }; > + > + arm_smmu_write_entry(&ste_writer.writer, ste->data, target->data); > + > + /* It's likely that we'll want to use the new STE soon */ > + if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH)) { > + struct arm_smmu_cmdq_ent > + prefetch_cmd = { .opcode = CMDQ_OP_PREFETCH_CFG, > + .prefetch = { > + .sid = sid, > + } }; > + > + arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd); > + } > } > > static void arm_smmu_make_abort_ste(struct arm_smmu_ste *target) > -- > 2.43.2 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E384C4345F for ; Fri, 19 Apr 2024 21:02:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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d2VkLWJ5OiBNaWNoYWVsIFNoYXZpdCA8bXNoYXZpdEBnb29nbGUuY29tPgo+IFRlc3RlZC1ieTog Tmljb2xpbiBDaGVuIDxuaWNvbGluY0BudmlkaWEuY29tPgo+IFRlc3RlZC1ieTogU2hhbWVlciBL b2xvdGh1bSA8c2hhbWVlcmFsaS5rb2xvdGh1bS50aG9kaUBodWF3ZWkuY29tPgo+IFNpZ25lZC1v ZmYtYnk6IEphc29uIEd1bnRob3JwZSA8amdnQG52aWRpYS5jb20+Cj4gLS0tCj4gIGRyaXZlcnMv aW9tbXUvYXJtL2FybS1zbW11LXYzL2FybS1zbW11LXYzLmMgfCAxNzggKysrKysrKysrKysrLS0t LS0tLS0KPiAgMSBmaWxlIGNoYW5nZWQsIDEwNiBpbnNlcnRpb25zKCspLCA3MiBkZWxldGlvbnMo LSkKPiAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9pb21tdS9hcm0vYXJtLXNtbXUtdjMvYXJtLXNt bXUtdjMuYyBiL2RyaXZlcnMvaW9tbXUvYXJtL2FybS1zbW11LXYzL2FybS1zbW11LXYzLmMKPiBp bmRleCA3OWMxOGU5NWRkMjkzZS4uYmYxMDVlOTE0ZDM4YjEgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVy cy9pb21tdS9hcm0vYXJtLXNtbXUtdjMvYXJtLXNtbXUtdjMuYwo+ICsrKyBiL2RyaXZlcnMvaW9t bXUvYXJtL2FybS1zbW11LXYzL2FybS1zbW11LXYzLmMKPiBAQCAtNDIsOCArNDIsMjAgQEAgZW51 bSBhcm1fc21tdV9tc2lfaW5kZXggewo+ICAJQVJNX1NNTVVfTUFYX01TSVMsCj4gIH07Cj4gIAo+ IC1zdGF0aWMgdm9pZCBhcm1fc21tdV9zeW5jX3N0ZV9mb3Jfc2lkKHN0cnVjdCBhcm1fc21tdV9k ZXZpY2UgKnNtbXUsCj4gLQkJCQkgICAgICBpb2FzaWRfdCBzaWQpOwo+ICtzdHJ1Y3QgYXJtX3Nt bXVfZW50cnlfd3JpdGVyX29wczsKPiArc3RydWN0IGFybV9zbW11X2VudHJ5X3dyaXRlciB7Cj4g Kwljb25zdCBzdHJ1Y3QgYXJtX3NtbXVfZW50cnlfd3JpdGVyX29wcyAqb3BzOwo+ICsJc3RydWN0 IGFybV9zbW11X21hc3RlciAqbWFzdGVyOwo+ICt9Owo+ICsKPiArc3RydWN0IGFybV9zbW11X2Vu dHJ5X3dyaXRlcl9vcHMgewo+ICsJX19sZTY0IHZfYml0Owo+ICsJdm9pZCAoKmdldF91c2VkKShj b25zdCBfX2xlNjQgKmVudHJ5LCBfX2xlNjQgKnVzZWQpOwo+ICsJdm9pZCAoKnN5bmMpKHN0cnVj dCBhcm1fc21tdV9lbnRyeV93cml0ZXIgKndyaXRlcik7Cj4gK307Cj4gKwo+ICsjZGVmaW5lIE5V TV9FTlRSWV9RV09SRFMgOAo+ICtzdGF0aWNfYXNzZXJ0KHNpemVvZihzdHJ1Y3QgYXJtX3NtbXVf c3RlKSA9PSBOVU1fRU5UUllfUVdPUkRTICogc2l6ZW9mKHU2NCkpOwo+ICAKPiAgc3RhdGljIHBo eXNfYWRkcl90IGFybV9zbW11X21zaV9jZmdbQVJNX1NNTVVfTUFYX01TSVNdWzNdID0gewo+ICAJ W0VWVFFfTVNJX0lOREVYXSA9IHsKPiBAQCAtOTcyLDQzICs5ODQsNDIgQEAgdm9pZCBhcm1fc21t dV90bGJfaW52X2FzaWQoc3RydWN0IGFybV9zbW11X2RldmljZSAqc21tdSwgdTE2IGFzaWQpCj4g ICAqIHdvdWxkIGJlIG5pY2UgaWYgdGhpcyB3YXMgY29tcGxldGUgYWNjb3JkaW5nIHRvIHRoZSBz cGVjLCBidXQgbWluaW1hbGx5IGl0Cj4gICAqIGhhcyB0byBjYXB0dXJlIHRoZSBiaXRzIHRoaXMg ZHJpdmVyIHVzZXMuCj4gICAqLwo+IC1zdGF0aWMgdm9pZCBhcm1fc21tdV9nZXRfc3RlX3VzZWQo Y29uc3Qgc3RydWN0IGFybV9zbW11X3N0ZSAqZW50LAo+IC0JCQkJICBzdHJ1Y3QgYXJtX3NtbXVf c3RlICp1c2VkX2JpdHMpCj4gK3N0YXRpYyB2b2lkIGFybV9zbW11X2dldF9zdGVfdXNlZChjb25z dCBfX2xlNjQgKmVudCwgX19sZTY0ICp1c2VkX2JpdHMpCj4gIHsKPiAtCXVuc2lnbmVkIGludCBj ZmcgPSBGSUVMRF9HRVQoU1RSVEFCX1NURV8wX0NGRywgbGU2NF90b19jcHUoZW50LT5kYXRhWzBd KSk7Cj4gKwl1bnNpZ25lZCBpbnQgY2ZnID0gRklFTERfR0VUKFNUUlRBQl9TVEVfMF9DRkcsIGxl NjRfdG9fY3B1KGVudFswXSkpOwo+ICAKPiAtCXVzZWRfYml0cy0+ZGF0YVswXSA9IGNwdV90b19s ZTY0KFNUUlRBQl9TVEVfMF9WKTsKPiAtCWlmICghKGVudC0+ZGF0YVswXSAmIGNwdV90b19sZTY0 KFNUUlRBQl9TVEVfMF9WKSkpCj4gKwl1c2VkX2JpdHNbMF0gPSBjcHVfdG9fbGU2NChTVFJUQUJf U1RFXzBfVik7Cj4gKwlpZiAoIShlbnRbMF0gJiBjcHVfdG9fbGU2NChTVFJUQUJfU1RFXzBfVikp KQo+ICAJCXJldHVybjsKPiAgCj4gLQl1c2VkX2JpdHMtPmRhdGFbMF0gfD0gY3B1X3RvX2xlNjQo U1RSVEFCX1NURV8wX0NGRyk7Cj4gKwl1c2VkX2JpdHNbMF0gfD0gY3B1X3RvX2xlNjQoU1RSVEFC X1NURV8wX0NGRyk7Cj4gIAo+ICAJLyogUzEgdHJhbnNsYXRlcyAqLwo+ICAJaWYgKGNmZyAmIEJJ VCgwKSkgewo+IC0JCXVzZWRfYml0cy0+ZGF0YVswXSB8PSBjcHVfdG9fbGU2NChTVFJUQUJfU1RF XzBfUzFGTVQgfAo+IC0JCQkJCQkgIFNUUlRBQl9TVEVfMF9TMUNUWFBUUl9NQVNLIHwKPiAtCQkJ CQkJICBTVFJUQUJfU1RFXzBfUzFDRE1BWCk7Cj4gLQkJdXNlZF9iaXRzLT5kYXRhWzFdIHw9Cj4g KwkJdXNlZF9iaXRzWzBdIHw9IGNwdV90b19sZTY0KFNUUlRBQl9TVEVfMF9TMUZNVCB8Cj4gKwkJ CQkJICAgIFNUUlRBQl9TVEVfMF9TMUNUWFBUUl9NQVNLIHwKPiArCQkJCQkgICAgU1RSVEFCX1NU RV8wX1MxQ0RNQVgpOwo+ICsJCXVzZWRfYml0c1sxXSB8PQo+ICAJCQljcHVfdG9fbGU2NChTVFJU QUJfU1RFXzFfUzFEU1MgfCBTVFJUQUJfU1RFXzFfUzFDSVIgfAo+ICAJCQkJICAgIFNUUlRBQl9T VEVfMV9TMUNPUiB8IFNUUlRBQl9TVEVfMV9TMUNTSCB8Cj4gIAkJCQkgICAgU1RSVEFCX1NURV8x X1MxU1RBTExEIHwgU1RSVEFCX1NURV8xX1NUUlcgfAo+ICAJCQkJICAgIFNUUlRBQl9TVEVfMV9F QVRTKTsKPiAtCQl1c2VkX2JpdHMtPmRhdGFbMl0gfD0gY3B1X3RvX2xlNjQoU1RSVEFCX1NURV8y X1MyVk1JRCk7Cj4gKwkJdXNlZF9iaXRzWzJdIHw9IGNwdV90b19sZTY0KFNUUlRBQl9TVEVfMl9T MlZNSUQpOwo+ICAJfQo+ICAKPiAgCS8qIFMyIHRyYW5zbGF0ZXMgKi8KPiAgCWlmIChjZmcgJiBC SVQoMSkpIHsKPiAtCQl1c2VkX2JpdHMtPmRhdGFbMV0gfD0KPiArCQl1c2VkX2JpdHNbMV0gfD0K PiAgCQkJY3B1X3RvX2xlNjQoU1RSVEFCX1NURV8xX0VBVFMgfCBTVFJUQUJfU1RFXzFfU0hDRkcp Owo+IC0JCXVzZWRfYml0cy0+ZGF0YVsyXSB8PQo+ICsJCXVzZWRfYml0c1syXSB8PQo+ICAJCQlj cHVfdG9fbGU2NChTVFJUQUJfU1RFXzJfUzJWTUlEIHwgU1RSVEFCX1NURV8yX1ZUQ1IgfAo+ICAJ CQkJICAgIFNUUlRBQl9TVEVfMl9TMkFBNjQgfCBTVFJUQUJfU1RFXzJfUzJFTkRJIHwKPiAgCQkJ CSAgICBTVFJUQUJfU1RFXzJfUzJQVFcgfCBTVFJUQUJfU1RFXzJfUzJSKTsKPiAtCQl1c2VkX2Jp dHMtPmRhdGFbM10gfD0gY3B1X3RvX2xlNjQoU1RSVEFCX1NURV8zX1MyVFRCX01BU0spOwo+ICsJ CXVzZWRfYml0c1szXSB8PSBjcHVfdG9fbGU2NChTVFJUQUJfU1RFXzNfUzJUVEJfTUFTSyk7Cj4g IAl9Cj4gIAo+ICAJaWYgKGNmZyA9PSBTVFJUQUJfU1RFXzBfQ0ZHX0JZUEFTUykKPiAtCQl1c2Vk X2JpdHMtPmRhdGFbMV0gfD0gY3B1X3RvX2xlNjQoU1RSVEFCX1NURV8xX1NIQ0ZHKTsKPiArCQl1 c2VkX2JpdHNbMV0gfD0gY3B1X3RvX2xlNjQoU1RSVEFCX1NURV8xX1NIQ0ZHKTsKPiAgfQo+ICAK PiAgLyoKPiBAQCAtMTAxNyw1NyArMTAyOCw1NSBAQCBzdGF0aWMgdm9pZCBhcm1fc21tdV9nZXRf c3RlX3VzZWQoY29uc3Qgc3RydWN0IGFybV9zbW11X3N0ZSAqZW50LAo+ICAgKiB1bnVzZWRfdXBk YXRlIGlzIGFuIGludGVybWVkaWF0ZSB2YWx1ZSBvZiBlbnRyeSB0aGF0IGhhcyB1bnVzZWQgYml0 cyBzZXQgdG8KPiAgICogdGhlaXIgbmV3IHZhbHVlcy4KPiAgICovCj4gLXN0YXRpYyB1OCBhcm1f c21tdV9lbnRyeV9xd29yZF9kaWZmKGNvbnN0IHN0cnVjdCBhcm1fc21tdV9zdGUgKmVudHJ5LAo+ IC0JCQkJICAgIGNvbnN0IHN0cnVjdCBhcm1fc21tdV9zdGUgKnRhcmdldCwKPiAtCQkJCSAgICBz dHJ1Y3QgYXJtX3NtbXVfc3RlICp1bnVzZWRfdXBkYXRlKQo+ICtzdGF0aWMgdTggYXJtX3NtbXVf ZW50cnlfcXdvcmRfZGlmZihzdHJ1Y3QgYXJtX3NtbXVfZW50cnlfd3JpdGVyICp3cml0ZXIsCj4g KwkJCQkgICAgY29uc3QgX19sZTY0ICplbnRyeSwgY29uc3QgX19sZTY0ICp0YXJnZXQsCj4gKwkJ CQkgICAgX19sZTY0ICp1bnVzZWRfdXBkYXRlKQo+ICB7Cj4gLQlzdHJ1Y3QgYXJtX3NtbXVfc3Rl IHRhcmdldF91c2VkID0ge307Cj4gLQlzdHJ1Y3QgYXJtX3NtbXVfc3RlIGN1cl91c2VkID0ge307 Cj4gKwlfX2xlNjQgdGFyZ2V0X3VzZWRbTlVNX0VOVFJZX1FXT1JEU10gPSB7fTsKPiArCV9fbGU2 NCBjdXJfdXNlZFtOVU1fRU5UUllfUVdPUkRTXSA9IHt9Owo+ICAJdTggdXNlZF9xd29yZF9kaWZm ID0gMDsKPiAgCXVuc2lnbmVkIGludCBpOwo+ICAKPiAtCWFybV9zbW11X2dldF9zdGVfdXNlZChl bnRyeSwgJmN1cl91c2VkKTsKPiAtCWFybV9zbW11X2dldF9zdGVfdXNlZCh0YXJnZXQsICZ0YXJn ZXRfdXNlZCk7Cj4gKwl3cml0ZXItPm9wcy0+Z2V0X3VzZWQoZW50cnksIGN1cl91c2VkKTsKPiAr CXdyaXRlci0+b3BzLT5nZXRfdXNlZCh0YXJnZXQsIHRhcmdldF91c2VkKTsKPiAgCj4gLQlmb3Ig KGkgPSAwOyBpICE9IEFSUkFZX1NJWkUodGFyZ2V0X3VzZWQuZGF0YSk7IGkrKykgewo+ICsJZm9y IChpID0gMDsgaSAhPSBOVU1fRU5UUllfUVdPUkRTOyBpKyspIHsKPiAgCQkvKgo+ICAJCSAqIENo ZWNrIHRoYXQgbWFza3MgYXJlIHVwIHRvIGRhdGUsIHRoZSBtYWtlIGZ1bmN0aW9ucyBhcmUgbm90 Cj4gIAkJICogYWxsb3dlZCB0byBzZXQgYSBiaXQgdG8gMSBpZiB0aGUgdXNlZCBmdW5jdGlvbiBk b2Vzbid0IHNheSBpdAo+ICAJCSAqIGlzIHVzZWQuCj4gIAkJICovCj4gLQkJV0FSTl9PTl9PTkNF KHRhcmdldC0+ZGF0YVtpXSAmIH50YXJnZXRfdXNlZC5kYXRhW2ldKTsKPiArCQlXQVJOX09OX09O Q0UodGFyZ2V0W2ldICYgfnRhcmdldF91c2VkW2ldKTsKPiAgCj4gIAkJLyogQml0cyBjYW4gY2hh bmdlIGJlY2F1c2UgdGhleSBhcmUgbm90IGN1cnJlbnRseSBiZWluZyB1c2VkICovCj4gLQkJdW51 c2VkX3VwZGF0ZS0+ZGF0YVtpXSA9IChlbnRyeS0+ZGF0YVtpXSAmIGN1cl91c2VkLmRhdGFbaV0p IHwKPiAtCQkJCQkgKHRhcmdldC0+ZGF0YVtpXSAmIH5jdXJfdXNlZC5kYXRhW2ldKTsKPiArCQl1 bnVzZWRfdXBkYXRlW2ldID0gKGVudHJ5W2ldICYgY3VyX3VzZWRbaV0pIHwKPiArCQkJCSAgICh0 YXJnZXRbaV0gJiB+Y3VyX3VzZWRbaV0pOwo+ICAJCS8qCj4gIAkJICogRWFjaCBiaXQgaW5kaWNh dGVzIHRoYXQgYSB1c2VkIGJpdCBpbiBhIHF3b3JkIG5lZWRzIHRvIGJlCj4gIAkJICogY2hhbmdl ZCBhZnRlciB1bnVzZWRfdXBkYXRlIGlzIGFwcGxpZWQuCj4gIAkJICovCj4gLQkJaWYgKCh1bnVz ZWRfdXBkYXRlLT5kYXRhW2ldICYgdGFyZ2V0X3VzZWQuZGF0YVtpXSkgIT0KPiAtCQkgICAgdGFy Z2V0LT5kYXRhW2ldKQo+ICsJCWlmICgodW51c2VkX3VwZGF0ZVtpXSAmIHRhcmdldF91c2VkW2ld KSAhPSB0YXJnZXRbaV0pCj4gIAkJCXVzZWRfcXdvcmRfZGlmZiB8PSAxIDw8IGk7Cj4gIAl9Cj4g IAlyZXR1cm4gdXNlZF9xd29yZF9kaWZmOwo+ICB9Cj4gIAo+IC1zdGF0aWMgYm9vbCBlbnRyeV9z ZXQoc3RydWN0IGFybV9zbW11X2RldmljZSAqc21tdSwgaW9hc2lkX3Qgc2lkLAo+IC0JCSAgICAg IHN0cnVjdCBhcm1fc21tdV9zdGUgKmVudHJ5LAo+IC0JCSAgICAgIGNvbnN0IHN0cnVjdCBhcm1f c21tdV9zdGUgKnRhcmdldCwgdW5zaWduZWQgaW50IHN0YXJ0LAo+ICtzdGF0aWMgYm9vbCBlbnRy eV9zZXQoc3RydWN0IGFybV9zbW11X2VudHJ5X3dyaXRlciAqd3JpdGVyLCBfX2xlNjQgKmVudHJ5 LAo+ICsJCSAgICAgIGNvbnN0IF9fbGU2NCAqdGFyZ2V0LCB1bnNpZ25lZCBpbnQgc3RhcnQsCj4g IAkJICAgICAgdW5zaWduZWQgaW50IGxlbikKPiAgewo+ICAJYm9vbCBjaGFuZ2VkID0gZmFsc2U7 Cj4gIAl1bnNpZ25lZCBpbnQgaTsKPiAgCj4gIAlmb3IgKGkgPSBzdGFydDsgbGVuICE9IDA7IGxl bi0tLCBpKyspIHsKPiAtCQlpZiAoZW50cnktPmRhdGFbaV0gIT0gdGFyZ2V0LT5kYXRhW2ldKSB7 Cj4gLQkJCVdSSVRFX09OQ0UoZW50cnktPmRhdGFbaV0sIHRhcmdldC0+ZGF0YVtpXSk7Cj4gKwkJ aWYgKGVudHJ5W2ldICE9IHRhcmdldFtpXSkgewo+ICsJCQlXUklURV9PTkNFKGVudHJ5W2ldLCB0 YXJnZXRbaV0pOwo+ICAJCQljaGFuZ2VkID0gdHJ1ZTsKPiAgCQl9Cj4gIAl9Cj4gIAo+ICAJaWYg KGNoYW5nZWQpCj4gLQkJYXJtX3NtbXVfc3luY19zdGVfZm9yX3NpZChzbW11LCBzaWQpOwo+ICsJ CXdyaXRlci0+b3BzLT5zeW5jKHdyaXRlcik7Cj4gIAlyZXR1cm4gY2hhbmdlZDsKPiAgfQo+ICAK PiBAQCAtMTA5NywyNCArMTEwNiwyMSBAQCBzdGF0aWMgYm9vbCBlbnRyeV9zZXQoc3RydWN0IGFy bV9zbW11X2RldmljZSAqc21tdSwgaW9hc2lkX3Qgc2lkLAo+ICAgKiBWPTAgcHJvY2Vzcy4gVGhp cyByZWxpZXMgb24gdGhlIElHTk9SRUQgYmVoYXZpb3IgZGVzY3JpYmVkIGluIHRoZQo+ICAgKiBz cGVjaWZpY2F0aW9uLgo+ICAgKi8KPiAtc3RhdGljIHZvaWQgYXJtX3NtbXVfd3JpdGVfc3RlKHN0 cnVjdCBhcm1fc21tdV9tYXN0ZXIgKm1hc3RlciwgdTMyIHNpZCwKPiAtCQkJICAgICAgIHN0cnVj dCBhcm1fc21tdV9zdGUgKmVudHJ5LAo+IC0JCQkgICAgICAgY29uc3Qgc3RydWN0IGFybV9zbW11 X3N0ZSAqdGFyZ2V0KQo+ICtzdGF0aWMgdm9pZCBhcm1fc21tdV93cml0ZV9lbnRyeShzdHJ1Y3Qg YXJtX3NtbXVfZW50cnlfd3JpdGVyICp3cml0ZXIsCj4gKwkJCQkgX19sZTY0ICplbnRyeSwgY29u c3QgX19sZTY0ICp0YXJnZXQpCj4gIHsKPiAtCXVuc2lnbmVkIGludCBudW1fZW50cnlfcXdvcmRz ID0gQVJSQVlfU0laRSh0YXJnZXQtPmRhdGEpOwo+IC0Jc3RydWN0IGFybV9zbW11X2RldmljZSAq c21tdSA9IG1hc3Rlci0+c21tdTsKPiAtCXN0cnVjdCBhcm1fc21tdV9zdGUgdW51c2VkX3VwZGF0 ZTsKPiArCV9fbGU2NCB1bnVzZWRfdXBkYXRlW05VTV9FTlRSWV9RV09SRFNdOwo+ICAJdTggdXNl ZF9xd29yZF9kaWZmOwo+ICAKPiAgCXVzZWRfcXdvcmRfZGlmZiA9Cj4gLQkJYXJtX3NtbXVfZW50 cnlfcXdvcmRfZGlmZihlbnRyeSwgdGFyZ2V0LCAmdW51c2VkX3VwZGF0ZSk7Cj4gKwkJYXJtX3Nt bXVfZW50cnlfcXdvcmRfZGlmZih3cml0ZXIsIGVudHJ5LCB0YXJnZXQsIHVudXNlZF91cGRhdGUp Owo+ICAJaWYgKGh3ZWlnaHQ4KHVzZWRfcXdvcmRfZGlmZikgPT0gMSkgewo+ICAJCS8qCj4gIAkJ ICogT25seSBvbmUgcXdvcmQgbmVlZHMgaXRzIHVzZWQgYml0cyB0byBiZSBjaGFuZ2VkLiBUaGlz IGlzIGEKPiAtCQkgKiBoaXRsZXNzIHVwZGF0ZSwgdXBkYXRlIGFsbCBiaXRzIHRoZSBjdXJyZW50 IFNURSBpcyBpZ25vcmluZwo+IC0JCSAqIHRvIHRoZWlyIG5ldyB2YWx1ZXMsIHRoZW4gdXBkYXRl IGEgc2luZ2xlICJjcml0aWNhbCBxd29yZCIgdG8KPiAtCQkgKiBjaGFuZ2UgdGhlIFNURSBhbmQg ZmluYWxseSAwIG91dCBhbnkgYml0cyB0aGF0IGFyZSBub3cgdW51c2VkCj4gLQkJICogaW4gdGhl IHRhcmdldCBjb25maWd1cmF0aW9uLgo+ICsJCSAqIGhpdGxlc3MgdXBkYXRlLCB1cGRhdGUgYWxs IGJpdHMgdGhlIGN1cnJlbnQgU1RFL0NEIGlzCj4gKwkJICogaWdub3JpbmcgdG8gdGhlaXIgbmV3 IHZhbHVlcywgdGhlbiB1cGRhdGUgYSBzaW5nbGUgImNyaXRpY2FsCj4gKwkJICogcXdvcmQiIHRv IGNoYW5nZSB0aGUgU1RFL0NEIGFuZCBmaW5hbGx5IDAgb3V0IGFueSBiaXRzIHRoYXQKPiArCQkg KiBhcmUgbm93IHVudXNlZCBpbiB0aGUgdGFyZ2V0IGNvbmZpZ3VyYXRpb24uCj4gIAkJICovCj4g IAkJdW5zaWduZWQgaW50IGNyaXRpY2FsX3F3b3JkX2luZGV4ID0gZmZzKHVzZWRfcXdvcmRfZGlm ZikgLSAxOwo+ICAKPiBAQCAtMTEyMywyMiArMTEyOSwyMSBAQCBzdGF0aWMgdm9pZCBhcm1fc21t dV93cml0ZV9zdGUoc3RydWN0IGFybV9zbW11X21hc3RlciAqbWFzdGVyLCB1MzIgc2lkLAo+ICAJ CSAqIHdyaXRpbmcgaXQgaW4gdGhlIG5leHQgc3RlcCBhbnl3YXlzLiBUaGlzIGNhbiBzYXZlIGEg c3luYwo+ICAJCSAqIHdoZW4gdGhlIG9ubHkgY2hhbmdlIGlzIGluIHRoYXQgcXdvcmQuCj4gIAkJ ICovCj4gLQkJdW51c2VkX3VwZGF0ZS5kYXRhW2NyaXRpY2FsX3F3b3JkX2luZGV4XSA9Cj4gLQkJ CWVudHJ5LT5kYXRhW2NyaXRpY2FsX3F3b3JkX2luZGV4XTsKPiAtCQllbnRyeV9zZXQoc21tdSwg c2lkLCBlbnRyeSwgJnVudXNlZF91cGRhdGUsIDAsIG51bV9lbnRyeV9xd29yZHMpOwo+IC0JCWVu dHJ5X3NldChzbW11LCBzaWQsIGVudHJ5LCB0YXJnZXQsIGNyaXRpY2FsX3F3b3JkX2luZGV4LCAx KTsKPiAtCQllbnRyeV9zZXQoc21tdSwgc2lkLCBlbnRyeSwgdGFyZ2V0LCAwLCBudW1fZW50cnlf cXdvcmRzKTsKPiArCQl1bnVzZWRfdXBkYXRlW2NyaXRpY2FsX3F3b3JkX2luZGV4XSA9Cj4gKwkJ CWVudHJ5W2NyaXRpY2FsX3F3b3JkX2luZGV4XTsKPiArCQllbnRyeV9zZXQod3JpdGVyLCBlbnRy eSwgdW51c2VkX3VwZGF0ZSwgMCwgTlVNX0VOVFJZX1FXT1JEUyk7Cj4gKwkJZW50cnlfc2V0KHdy aXRlciwgZW50cnksIHRhcmdldCwgY3JpdGljYWxfcXdvcmRfaW5kZXgsIDEpOwo+ICsJCWVudHJ5 X3NldCh3cml0ZXIsIGVudHJ5LCB0YXJnZXQsIDAsIE5VTV9FTlRSWV9RV09SRFMpOwo+ICAJfSBl bHNlIGlmICh1c2VkX3F3b3JkX2RpZmYpIHsKPiAgCQkvKgo+ICAJCSAqIEF0IGxlYXN0IHR3byBx d29yZHMgbmVlZCB0aGVpciBpbnVzZSBiaXRzIHRvIGJlIGNoYW5nZWQuIFRoaXMKPiAgCQkgKiBy ZXF1aXJlcyBhIGJyZWFraW5nIHVwZGF0ZSwgemVybyB0aGUgViBiaXQsIHdyaXRlIGFsbCBxd29y ZHMKPiAgCQkgKiBidXQgMCwgdGhlbiBzZXQgcXdvcmQgMAo+ICAJCSAqLwo+IC0JCXVudXNlZF91 cGRhdGUuZGF0YVswXSA9IGVudHJ5LT5kYXRhWzBdICYKPiAtCQkJCQljcHVfdG9fbGU2NCh+U1RS VEFCX1NURV8wX1YpOwo+IC0JCWVudHJ5X3NldChzbW11LCBzaWQsIGVudHJ5LCAmdW51c2VkX3Vw ZGF0ZSwgMCwgMSk7Cj4gLQkJZW50cnlfc2V0KHNtbXUsIHNpZCwgZW50cnksIHRhcmdldCwgMSwg bnVtX2VudHJ5X3F3b3JkcyAtIDEpOwo+IC0JCWVudHJ5X3NldChzbW11LCBzaWQsIGVudHJ5LCB0 YXJnZXQsIDAsIDEpOwo+ICsJCXVudXNlZF91cGRhdGVbMF0gPSBlbnRyeVswXSAmICh+d3JpdGVy LT5vcHMtPnZfYml0KTsKCmFybV9zbW11X3dyaXRlX2VudHJ5KCkgYXNzdW1lcyB0aGF0IHZfYml0 IGlzIGluIGVudHJ5WzBdIGFuZCB0aGF0IOKAnDHigJ0gbWVhbnMgdmFsaWQKKHdoaWNoIGlzIHRy dWUgZm9yIGJvdGggU1RFIGFuZCBDRCkgc28gd2h5IGRvIHdlIGNhcmUgYWJvdXQgaXQsIGlmIHdl IGJyZWFrIHRoZQpTVEUvQ0QgYW55d2F5LCB3aHkgbm90IGp1c3QgZG86CgoJdW51c2VkX3VwZGF0 ZVswXSA9IDA7CgllbnRyeV9zZXQod3JpdGVyLCBlbnRyeSwgdW51c2VkX3VwZGF0ZSwgMCwgMSk7 CgllbnRyeV9zZXQod3JpdGVyLCBlbnRyeSwgdGFyZ2V0LCAxLCBOVU1fRU5UUllfUVdPUkRTIC0g MSkKCWVudHJ5X3NldCh3cml0ZXIsIGVudHJ5LCB0YXJnZXQsIDAsIDEpOwoKVGhhdCBtYWtlcyB0 aGUgY29kZSBzaW1wbGVyIGJ5IGF2b2lkaW5nIGhhdmluZyB0aGUgdl9iaXQgaW4KYXJtX3NtbXVf ZW50cnlfd3JpdGVyX29wcy4KCgpUaGFua3MsCk1vc3RhZmEKCj4gKwkJZW50cnlfc2V0KHdyaXRl ciwgZW50cnksIHVudXNlZF91cGRhdGUsIDAsIDEpOwo+ICsJCWVudHJ5X3NldCh3cml0ZXIsIGVu dHJ5LCB0YXJnZXQsIDEsIE5VTV9FTlRSWV9RV09SRFMgLSAxKTsKPiArCQllbnRyeV9zZXQod3Jp dGVyLCBlbnRyeSwgdGFyZ2V0LCAwLCAxKTsKPiAgCX0gZWxzZSB7Cj4gIAkJLyoKPiAgCQkgKiBO byBpbnVzZSBiaXQgY2hhbmdlZC4gU2FuaXR5IGNoZWNrIHRoYXQgYWxsIHVudXNlZCBiaXRzIGFy ZSAwCj4gQEAgLTExNDYsMTggKzExNTEsNyBAQCBzdGF0aWMgdm9pZCBhcm1fc21tdV93cml0ZV9z dGUoc3RydWN0IGFybV9zbW11X21hc3RlciAqbWFzdGVyLCB1MzIgc2lkLAo+ICAJCSAqIGNvbXB1 dGVfcXdvcmRfZGlmZigpLgo+ICAJCSAqLwo+ICAJCVdBUk5fT05fT05DRSgKPiAtCQkJZW50cnlf c2V0KHNtbXUsIHNpZCwgZW50cnksIHRhcmdldCwgMCwgbnVtX2VudHJ5X3F3b3JkcykpOwo+IC0J fQo+IC0KPiAtCS8qIEl0J3MgbGlrZWx5IHRoYXQgd2UnbGwgd2FudCB0byB1c2UgdGhlIG5ldyBT VEUgc29vbiAqLwo+IC0JaWYgKCEoc21tdS0+b3B0aW9ucyAmIEFSTV9TTU1VX09QVF9TS0lQX1BS RUZFVENIKSkgewo+IC0JCXN0cnVjdCBhcm1fc21tdV9jbWRxX2VudAo+IC0JCQlwcmVmZXRjaF9j bWQgPSB7IC5vcGNvZGUgPSBDTURRX09QX1BSRUZFVENIX0NGRywKPiAtCQkJCQkgLnByZWZldGNo ID0gewo+IC0JCQkJCQkgLnNpZCA9IHNpZCwKPiAtCQkJCQkgfSB9Owo+IC0KPiAtCQlhcm1fc21t dV9jbWRxX2lzc3VlX2NtZChzbW11LCAmcHJlZmV0Y2hfY21kKTsKPiArCQkJZW50cnlfc2V0KHdy aXRlciwgZW50cnksIHRhcmdldCwgMCwgTlVNX0VOVFJZX1FXT1JEUykpOwo+ICAJfQo+ICB9Cj4g IAo+IEBAIC0xNDMwLDE3ICsxNDI0LDU3IEBAIGFybV9zbW11X3dyaXRlX3N0cnRhYl9sMV9kZXNj KF9fbGU2NCAqZHN0LCBzdHJ1Y3QgYXJtX3NtbXVfc3RydGFiX2wxX2Rlc2MgKmRlc2MpCj4gIAlX UklURV9PTkNFKCpkc3QsIGNwdV90b19sZTY0KHZhbCkpOwo+ICB9Cj4gIAo+IC1zdGF0aWMgdm9p ZCBhcm1fc21tdV9zeW5jX3N0ZV9mb3Jfc2lkKHN0cnVjdCBhcm1fc21tdV9kZXZpY2UgKnNtbXUs IHUzMiBzaWQpCj4gK3N0cnVjdCBhcm1fc21tdV9zdGVfd3JpdGVyIHsKPiArCXN0cnVjdCBhcm1f c21tdV9lbnRyeV93cml0ZXIgd3JpdGVyOwo+ICsJdTMyIHNpZDsKPiArfTsKPiArCj4gK3N0YXRp YyB2b2lkIGFybV9zbW11X3N0ZV93cml0ZXJfc3luY19lbnRyeShzdHJ1Y3QgYXJtX3NtbXVfZW50 cnlfd3JpdGVyICp3cml0ZXIpCj4gIHsKPiArCXN0cnVjdCBhcm1fc21tdV9zdGVfd3JpdGVyICpz dGVfd3JpdGVyID0KPiArCQljb250YWluZXJfb2Yod3JpdGVyLCBzdHJ1Y3QgYXJtX3NtbXVfc3Rl X3dyaXRlciwgd3JpdGVyKTsKPiAgCXN0cnVjdCBhcm1fc21tdV9jbWRxX2VudCBjbWQgPSB7Cj4g IAkJLm9wY29kZQk9IENNRFFfT1BfQ0ZHSV9TVEUsCj4gIAkJLmNmZ2kJPSB7Cj4gLQkJCS5zaWQJ PSBzaWQsCj4gKwkJCS5zaWQJPSBzdGVfd3JpdGVyLT5zaWQsCj4gIAkJCS5sZWFmCT0gdHJ1ZSwK PiAgCQl9LAo+ICAJfTsKPiAgCj4gLQlhcm1fc21tdV9jbWRxX2lzc3VlX2NtZF93aXRoX3N5bmMo c21tdSwgJmNtZCk7Cj4gKwlhcm1fc21tdV9jbWRxX2lzc3VlX2NtZF93aXRoX3N5bmMod3JpdGVy LT5tYXN0ZXItPnNtbXUsICZjbWQpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IGFy bV9zbW11X2VudHJ5X3dyaXRlcl9vcHMgYXJtX3NtbXVfc3RlX3dyaXRlcl9vcHMgPSB7Cj4gKwku c3luYyA9IGFybV9zbW11X3N0ZV93cml0ZXJfc3luY19lbnRyeSwKPiArCS5nZXRfdXNlZCA9IGFy bV9zbW11X2dldF9zdGVfdXNlZCwKPiArCS52X2JpdCA9IGNwdV90b19sZTY0KFNUUlRBQl9TVEVf MF9WKSwKPiArfTsKPiArCj4gK3N0YXRpYyB2b2lkIGFybV9zbW11X3dyaXRlX3N0ZShzdHJ1Y3Qg YXJtX3NtbXVfbWFzdGVyICptYXN0ZXIsIHUzMiBzaWQsCj4gKwkJCSAgICAgICBzdHJ1Y3QgYXJt X3NtbXVfc3RlICpzdGUsCj4gKwkJCSAgICAgICBjb25zdCBzdHJ1Y3QgYXJtX3NtbXVfc3RlICp0 YXJnZXQpCj4gK3sKPiArCXN0cnVjdCBhcm1fc21tdV9kZXZpY2UgKnNtbXUgPSBtYXN0ZXItPnNt bXU7Cj4gKwlzdHJ1Y3QgYXJtX3NtbXVfc3RlX3dyaXRlciBzdGVfd3JpdGVyID0gewo+ICsJCS53 cml0ZXIgPSB7Cj4gKwkJCS5vcHMgPSAmYXJtX3NtbXVfc3RlX3dyaXRlcl9vcHMsCj4gKwkJCS5t YXN0ZXIgPSBtYXN0ZXIsCj4gKwkJfSwKPiArCQkuc2lkID0gc2lkLAo+ICsJfTsKPiArCj4gKwlh cm1fc21tdV93cml0ZV9lbnRyeSgmc3RlX3dyaXRlci53cml0ZXIsIHN0ZS0+ZGF0YSwgdGFyZ2V0 LT5kYXRhKTsKPiArCj4gKwkvKiBJdCdzIGxpa2VseSB0aGF0IHdlJ2xsIHdhbnQgdG8gdXNlIHRo ZSBuZXcgU1RFIHNvb24gKi8KPiArCWlmICghKHNtbXUtPm9wdGlvbnMgJiBBUk1fU01NVV9PUFRf U0tJUF9QUkVGRVRDSCkpIHsKPiArCQlzdHJ1Y3QgYXJtX3NtbXVfY21kcV9lbnQKPiArCQkJcHJl ZmV0Y2hfY21kID0geyAub3Bjb2RlID0gQ01EUV9PUF9QUkVGRVRDSF9DRkcsCj4gKwkJCQkJIC5w cmVmZXRjaCA9IHsKPiArCQkJCQkJIC5zaWQgPSBzaWQsCj4gKwkJCQkJIH0gfTsKPiArCj4gKwkJ YXJtX3NtbXVfY21kcV9pc3N1ZV9jbWQoc21tdSwgJnByZWZldGNoX2NtZCk7Cj4gKwl9Cj4gIH0K PiAgCj4gIHN0YXRpYyB2b2lkIGFybV9zbW11X21ha2VfYWJvcnRfc3RlKHN0cnVjdCBhcm1fc21t dV9zdGUgKnRhcmdldCkKPiAtLSAKPiAyLjQzLjIKPiAKCl9fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fCmxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBsaXN0Cmxp bnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFk Lm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LWFybS1rZXJuZWwK