From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-182.mta0.migadu.com (out-182.mta0.migadu.com [91.218.175.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1980248CDD for ; Wed, 1 May 2024 05:43:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.182 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714542195; cv=none; b=ou+9p7fMJE9K4dsSg1du643kZgUaidnyDeD3/LDhZipapWDeojxUKBM2TxTfNyY4iyZ1upNsz6IT02vTsXjAYH3AbE3V+7osl3Ofxyjt/piBpKO0qGqnw4eQzeKmC9CV4ewWLmnZ4tI2D4k6QKmxTH1IpnixBf7a6ZRfifBbYFc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714542195; c=relaxed/simple; bh=26r+LT/6atmj9opecbx4FJ7PWFVD5JLfAoCCwRN2W1M=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=fMp3Tv+RSU9ihtffMrNL1Mts2+z8KXrMWl8+lLNCKxFN7ZXcOIU+aFgeOEcV9hQOjEXQ7xb8G1zbLhyOwmQu6idh91J6DV3Qzl/myIhIOxzaudOGwgnF+JTyCi+fDZvj9sAIKO+xOuKDFhv503kc/vEuxItH6gy3/hszPkO3scM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=jookia.org; spf=none smtp.mailfrom=jookia.org; dkim=pass (2048-bit key) header.d=jookia.org header.i=@jookia.org header.b=Y424BfbC; arc=none smtp.client-ip=91.218.175.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=jookia.org Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=jookia.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=jookia.org header.i=@jookia.org header.b="Y424BfbC" Date: Wed, 1 May 2024 15:42:44 +1000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1714542190; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=I0JjuJfRwN3PxzuU5OJDvRQPhrTURiBh6iup5xIVpTE=; b=Y424BfbCPAvaTiEHva+EjwrF+C76RSvznwiqdRgCuCqTxRnj4CPCMnZcgRxIj6IJHGoWfH QDA+QESm21J7Owl6Nwa43JtUtBul3458OjK+OWjihWPXsis2nkQ35huVIS2GaA+EYM92bo pSi6wkVCU6jXLeu40QYL6P5vfcGM/B1CzZr6tFHol2LsuCNthYca4DosTY7W8q/uO1Y0oB dsdOKMr7KJobIGPIBnci+tvmJ2r7NGGYg0swk/u4gxbde7uajDO3S8ZtWd1PLIOYmAUHX5 AVpikoE3IjpRbzcw/aqXp5G6Ink/LHb/tylAKunqkzV7dKkd1tifPeDv+/rSGQ== X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: John Watts To: Aleksandr Shubin Cc: linux-kernel@vger.kernel.org, Brandon Cheo Fusi , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Cristian Ciocaltea , Marc Kleine-Budde , Maksim Kiselev , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: Re: [PATCH v8 2/3] pwm: Add Allwinner's D1/T113-S3/R329 SoCs PWM support Message-ID: References: <20240131125920.2879433-1-privatesub2@gmail.com> <20240131125920.2879433-3-privatesub2@gmail.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240131125920.2879433-3-privatesub2@gmail.com> X-Migadu-Flow: FLOW_OUT Hi, On Wed, Jan 31, 2024 at 03:59:15PM +0300, Aleksandr Shubin wrote: > + if (state->polarity != pwm->state.polarity || > + state->duty_cycle != pwm->state.duty_cycle || > + state->period != pwm->state.period) { > + ctl = sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CTL(pwm->hwpwm)); > + clk_cfg = sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CLK_CFG(pwm->hwpwm)); > + hosc_rate = clk_get_rate(sun20i_chip->clk_hosc); > + bus_rate = clk_get_rate(sun20i_chip->clk_apb0); > + if (pwm_en & SUN20I_PWM_ENABLE_EN(pwm->hwpwm ^ 1)) { > + /* if the neighbor channel is enable, check period only */ > + use_bus_clk = FIELD_GET(SUN20I_PWM_CLK_CFG_SRC, clk_cfg) != 0; > + val = mul_u64_u64_div_u64(state->period, > + (use_bus_clk ? bus_rate : hosc_rate), > + NSEC_PER_SEC); > + > + div_m = FIELD_GET(SUN20I_PWM_CLK_CFG_DIV_M, clk_cfg); > + } else { > + /* check period and select clock source */ > + use_bus_clk = false; > + val = mul_u64_u64_div_u64(state->period, hosc_rate, NSEC_PER_SEC); > + if (val <= 1) { > + use_bus_clk = true; > + val = mul_u64_u64_div_u64(state->period, bus_rate, NSEC_PER_SEC); > + if (val <= 1) { > + ret = -EINVAL; > + goto unlock_mutex; > + } > + } > + div_m = fls(DIV_ROUND_DOWN_ULL(val, SUN20I_PWM_MAGIC)); > + if (div_m > SUN20I_PWM_CLK_DIV_M_MAX) { > + ret = -EINVAL; > + goto unlock_mutex; > + } > + > + /* set up the CLK_DIV_M and clock CLK_SRC */ > + clk_cfg = FIELD_PREP(SUN20I_PWM_CLK_CFG_DIV_M, div_m); > + clk_cfg |= FIELD_PREP(SUN20I_PWM_CLK_CFG_SRC, use_bus_clk); > + > + sun20i_pwm_writel(sun20i_chip, clk_cfg, SUN20I_PWM_CLK_CFG(pwm->hwpwm)); > + } If I'm reading this correctly, for each PWM pair you set the clock once. Wouldn't this mean that the order of setting PWMs would affect the accuracy? It would be good to note this down perhaps? John. > -- > 2.25.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B163BC19F53 for ; Wed, 1 May 2024 05:43:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Uki4AuPmJp+zMoWvKhetIosdTxr+R+RoyrDVm4mh/o8=; b=ezS4clJA/SKQz2 Pvdfd2mJyTUz0US7vCyyCIOEfm2gLZL0IQEkMM18skYrdu6N07+/CzQaJjYVB0dUpL5AO6HgkNPaL 7cX34C7uCwJXE3XBXsHScRfwS3Qe8n6dzSHB3YY1Q5eCZTTtZV1SD3pJ9lxzXv8oIjJVzTQPFx0Le +l7R1m1HbyRPF+xsA/q+WSoQBmWqkqbAsy4iBHzLJ+EDQMKTzfRqIzvgqW+Wm/NQYaz3/mv1r6efm /mGaKCiZllOZBY0Ab9u3VvZbeRj592idji2IXEmRo6r0tyv/HAPZEpOMnNJMEI9H3bBH7PVvDXN9M gVSQ+mXcx9KY3k2nptDg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s22kf-00000008dhu-3PZk; Wed, 01 May 2024 05:43:33 +0000 Received: from out-188.mta0.migadu.com ([91.218.175.188]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s22kW-00000008ddQ-2iA8 for linux-riscv@lists.infradead.org; Wed, 01 May 2024 05:43:32 +0000 Date: Wed, 1 May 2024 15:42:44 +1000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1714542190; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=I0JjuJfRwN3PxzuU5OJDvRQPhrTURiBh6iup5xIVpTE=; b=Y424BfbCPAvaTiEHva+EjwrF+C76RSvznwiqdRgCuCqTxRnj4CPCMnZcgRxIj6IJHGoWfH QDA+QESm21J7Owl6Nwa43JtUtBul3458OjK+OWjihWPXsis2nkQ35huVIS2GaA+EYM92bo pSi6wkVCU6jXLeu40QYL6P5vfcGM/B1CzZr6tFHol2LsuCNthYca4DosTY7W8q/uO1Y0oB dsdOKMr7KJobIGPIBnci+tvmJ2r7NGGYg0swk/u4gxbde7uajDO3S8ZtWd1PLIOYmAUHX5 AVpikoE3IjpRbzcw/aqXp5G6Ink/LHb/tylAKunqkzV7dKkd1tifPeDv+/rSGQ== X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: John Watts To: Aleksandr Shubin Subject: Re: [PATCH v8 2/3] pwm: Add Allwinner's D1/T113-S3/R329 SoCs PWM support Message-ID: References: <20240131125920.2879433-1-privatesub2@gmail.com> <20240131125920.2879433-3-privatesub2@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240131125920.2879433-3-privatesub2@gmail.com> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240430_224324_842828_E7EDE492 X-CRM114-Status: GOOD ( 15.33 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pwm@vger.kernel.org, Conor Dooley , Albert Ou , Philipp Zabel , Maksim Kiselev , Samuel Holland , Brandon Cheo Fusi , Paul Walmsley , linux-kernel@vger.kernel.org, Jernej Skrabec , Chen-Yu Tsai , Rob Herring , Palmer Dabbelt , linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Marc Kleine-Budde , linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Hi, On Wed, Jan 31, 2024 at 03:59:15PM +0300, Aleksandr Shubin wrote: > + if (state->polarity != pwm->state.polarity || > + state->duty_cycle != pwm->state.duty_cycle || > + state->period != pwm->state.period) { > + ctl = sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CTL(pwm->hwpwm)); > + clk_cfg = sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CLK_CFG(pwm->hwpwm)); > + hosc_rate = clk_get_rate(sun20i_chip->clk_hosc); > + bus_rate = clk_get_rate(sun20i_chip->clk_apb0); > + if (pwm_en & SUN20I_PWM_ENABLE_EN(pwm->hwpwm ^ 1)) { > + /* if the neighbor channel is enable, check period only */ > + use_bus_clk = FIELD_GET(SUN20I_PWM_CLK_CFG_SRC, clk_cfg) != 0; > + val = mul_u64_u64_div_u64(state->period, > + (use_bus_clk ? bus_rate : hosc_rate), > + NSEC_PER_SEC); > + > + div_m = FIELD_GET(SUN20I_PWM_CLK_CFG_DIV_M, clk_cfg); > + } else { > + /* check period and select clock source */ > + use_bus_clk = false; > + val = mul_u64_u64_div_u64(state->period, hosc_rate, NSEC_PER_SEC); > + if (val <= 1) { > + use_bus_clk = true; > + val = mul_u64_u64_div_u64(state->period, bus_rate, NSEC_PER_SEC); > + if (val <= 1) { > + ret = -EINVAL; > + goto unlock_mutex; > + } > + } > + div_m = fls(DIV_ROUND_DOWN_ULL(val, SUN20I_PWM_MAGIC)); > + if (div_m > SUN20I_PWM_CLK_DIV_M_MAX) { > + ret = -EINVAL; > + goto unlock_mutex; > + } > + > + /* set up the CLK_DIV_M and clock CLK_SRC */ > + clk_cfg = FIELD_PREP(SUN20I_PWM_CLK_CFG_DIV_M, div_m); > + clk_cfg |= FIELD_PREP(SUN20I_PWM_CLK_CFG_SRC, use_bus_clk); > + > + sun20i_pwm_writel(sun20i_chip, clk_cfg, SUN20I_PWM_CLK_CFG(pwm->hwpwm)); > + } If I'm reading this correctly, for each PWM pair you set the clock once. Wouldn't this mean that the order of setting PWMs would affect the accuracy? It would be good to note this down perhaps? John. > -- > 2.25.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2047FC4345F for ; Wed, 1 May 2024 05:43:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=cowMbrDGYo+ShEXpnAbH1IBHkVLfZearMJA7HLWI3bs=; b=tplCy5ljs0LB5K oIv7G20fdNfhWxZZFXw4rOCnBcGKtN9fsrDEnrWMng6aZEJ994LKMWA2x3jzAJT4qYlHoQqgHCmb4 dh99rZjZsCtOoCxaPt6z2eiXPhEjydfLJr/+cevA5PFoXOQDTR4Pq7wLr5xBGQfJbrNEPALRC65bp wlc1cMfxL85L939iIloWEDTtabUq9+9yW2QgtHbr5226FJ6Wvm4+C9VNkfCpAYtJTKzT55WduKZaR DvNOqHOMtUrI9J8vZSHaY6wqi5z+LbNt7u2852YSz7miXSeIMwlrXZSy1IuMzqDEEpoNMGHXJRRUA j3pblMmEL2lkw/3nupDw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s22ka-00000008dgs-4BcN; Wed, 01 May 2024 05:43:29 +0000 Received: from out-176.mta0.migadu.com ([2001:41d0:1004:224b::b0]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s22kT-00000008ddV-3Luv for linux-arm-kernel@lists.infradead.org; Wed, 01 May 2024 05:43:27 +0000 Date: Wed, 1 May 2024 15:42:44 +1000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jookia.org; s=key1; t=1714542190; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=I0JjuJfRwN3PxzuU5OJDvRQPhrTURiBh6iup5xIVpTE=; b=Y424BfbCPAvaTiEHva+EjwrF+C76RSvznwiqdRgCuCqTxRnj4CPCMnZcgRxIj6IJHGoWfH QDA+QESm21J7Owl6Nwa43JtUtBul3458OjK+OWjihWPXsis2nkQ35huVIS2GaA+EYM92bo pSi6wkVCU6jXLeu40QYL6P5vfcGM/B1CzZr6tFHol2LsuCNthYca4DosTY7W8q/uO1Y0oB dsdOKMr7KJobIGPIBnci+tvmJ2r7NGGYg0swk/u4gxbde7uajDO3S8ZtWd1PLIOYmAUHX5 AVpikoE3IjpRbzcw/aqXp5G6Ink/LHb/tylAKunqkzV7dKkd1tifPeDv+/rSGQ== X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: John Watts To: Aleksandr Shubin Cc: linux-kernel@vger.kernel.org, Brandon Cheo Fusi , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Cristian Ciocaltea , Marc Kleine-Budde , Maksim Kiselev , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: Re: [PATCH v8 2/3] pwm: Add Allwinner's D1/T113-S3/R329 SoCs PWM support Message-ID: References: <20240131125920.2879433-1-privatesub2@gmail.com> <20240131125920.2879433-3-privatesub2@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240131125920.2879433-3-privatesub2@gmail.com> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240430_224322_010201_A98761A3 X-CRM114-Status: GOOD ( 16.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On Wed, Jan 31, 2024 at 03:59:15PM +0300, Aleksandr Shubin wrote: > + if (state->polarity != pwm->state.polarity || > + state->duty_cycle != pwm->state.duty_cycle || > + state->period != pwm->state.period) { > + ctl = sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CTL(pwm->hwpwm)); > + clk_cfg = sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CLK_CFG(pwm->hwpwm)); > + hosc_rate = clk_get_rate(sun20i_chip->clk_hosc); > + bus_rate = clk_get_rate(sun20i_chip->clk_apb0); > + if (pwm_en & SUN20I_PWM_ENABLE_EN(pwm->hwpwm ^ 1)) { > + /* if the neighbor channel is enable, check period only */ > + use_bus_clk = FIELD_GET(SUN20I_PWM_CLK_CFG_SRC, clk_cfg) != 0; > + val = mul_u64_u64_div_u64(state->period, > + (use_bus_clk ? bus_rate : hosc_rate), > + NSEC_PER_SEC); > + > + div_m = FIELD_GET(SUN20I_PWM_CLK_CFG_DIV_M, clk_cfg); > + } else { > + /* check period and select clock source */ > + use_bus_clk = false; > + val = mul_u64_u64_div_u64(state->period, hosc_rate, NSEC_PER_SEC); > + if (val <= 1) { > + use_bus_clk = true; > + val = mul_u64_u64_div_u64(state->period, bus_rate, NSEC_PER_SEC); > + if (val <= 1) { > + ret = -EINVAL; > + goto unlock_mutex; > + } > + } > + div_m = fls(DIV_ROUND_DOWN_ULL(val, SUN20I_PWM_MAGIC)); > + if (div_m > SUN20I_PWM_CLK_DIV_M_MAX) { > + ret = -EINVAL; > + goto unlock_mutex; > + } > + > + /* set up the CLK_DIV_M and clock CLK_SRC */ > + clk_cfg = FIELD_PREP(SUN20I_PWM_CLK_CFG_DIV_M, div_m); > + clk_cfg |= FIELD_PREP(SUN20I_PWM_CLK_CFG_SRC, use_bus_clk); > + > + sun20i_pwm_writel(sun20i_chip, clk_cfg, SUN20I_PWM_CLK_CFG(pwm->hwpwm)); > + } If I'm reading this correctly, for each PWM pair you set the clock once. Wouldn't this mean that the order of setting PWMs would affect the accuracy? It would be good to note this down perhaps? John. > -- > 2.25.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel