Re: [PATCH v11 19/21] i386: Add cache topology info in CPUCacheInfo

[Zhao Liu <zhao1.liu@intel.com>]

Hi Tejus,

(Also +Paolo/Daniel)

On Tue, Apr 30, 2024 at 06:14:52AM +0000, Tejus GK wrote:
> Date: Tue, 30 Apr 2024 06:14:52 +0000
> From: Tejus GK <tejus.gk@nutanix.com>
> Subject: Re: [PATCH v11 19/21] i386: Add cache topology info in CPUCacheInfo
> 
> 
> 
> On 24 Apr 2024, at 9:19 PM, Zhao Liu <zhao1.liu@intel.com> wrote:
> 
> @@ -2140,6 +2164,7 @@ static const CPUCaches epyc_milan_cache_info = {
>         .lines_per_tag = 1,
>         .self_init = 1,
>         .no_invd_sharing = true,
> +        .share_level = CPU_TOPO_LEVEL_CORE,
>     },
>     .l1i_cache = &(CPUCacheInfo) {
>         .type = INSTRUCTION_CACHE,
> @@ -2152,6 +2177,7 @@ static const CPUCaches epyc_milan_cache_info = {
>         .lines_per_tag = 1,
>         .self_init = 1,
>         .no_invd_sharing = true,
> +        .share_level = CPU_TOPO_LEVEL_CORE,
>     },
>     .l2_cache = &(CPUCacheInfo) {
>         .type = UNIFIED_CACHE,
> @@ -2162,6 +2188,7 @@ static const CPUCaches epyc_milan_cache_info = {
>         .partitions = 1,
>         .sets = 1024,
>         .lines_per_tag = 1,
> +        .share_level = CPU_TOPO_LEVEL_CORE,
>     },
>     .l3_cache = &(CPUCacheInfo) {
>         .type = UNIFIED_CACHE,
> @@ -2175,6 +2202,7 @@ static const CPUCaches epyc_milan_cache_info = {
>         .self_init = true,
>         .inclusive = true,
>         .complex_indexing = true,
> +        .share_level = CPU_TOPO_LEVEL_DIE,
>     },
> };
> 
> 
> Hi Zhao and Babu, thank you for this patch. I have a slightly
> off-topic question about this patch. Firstly, many AMD CPU models
> have pre-defined cache sizes for the various cache levels; how are
> these values decided? I couldn't figure that out from the patches that
> introduced those changes.

I understand the AMD pre-defined cache idea started from this
discussion:

https://lore.kernel.org/qemu-devel/20180320175427.GU3417@localhost.localdomain/

From the discussion, it appears that AMD's cache information is encoded
according to the spec/datasheet for each generation of EPYC.

> Secondly, there isn't any pre-defined cache size for Intel, and the
> legacy cache values are used. This value can be vastly different from
> what actual available caches might be. Is there any reason why
> something like that for Intel has yet to be introduced?

Previously, there should be a lack of reason to introduce on Intel side,
or haven't met the relevant need/issue before.

I understand that AMD's reason is to make the cache information in the
Guest with a specific CPU model look more correct and to be able to
better emulate the Host environment.

Hi @Paolo and @Daniel, do you think Intel should also add correct cache
info for each CPU model?

Thanks,
Zhao