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From: Sean Christopherson <seanjc@google.com>
To: Rick P Edgecombe <rick.p.edgecombe@intel.com>
Cc: Chao Gao <chao.gao@intel.com>, Xiaoyao Li <xiaoyao.li@intel.com>,
	 "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	"pbonzini@redhat.com" <pbonzini@redhat.com>
Subject: Re: [RFC] TDX module configurability of 0x80000008
Date: Tue, 7 May 2024 09:21:41 -0700	[thread overview]
Message-ID: <ZjpVFa0vUMitP2wF@google.com> (raw)
In-Reply-To: <ee8c0227816d546a0a02f3db9519d289d3e275b0.camel@intel.com>

On Tue, May 07, 2024, Rick P Edgecombe wrote:
> On Tue, 2024-05-07 at 22:22 +0800, Chao Gao wrote:
> > > 2. There was some concern that exposing non-zero bits in [23:16] could
> > > confuse existing TDs. Of course KVM doesn't support any TDs today, but if
> > > this feature comes after initial KVM support for TDX and KVM wants to set
> > > it by default, then it could be an issue.
> > 
> > Do you mean some TDs may assert that [23:16] are 0s? A future-proof design
> > won't have this assertion. And this case (i.e., some CPUID bits become non-
> > zero) happens on every new generation of CPUs and doesn't confuse existing
> > OSes. I don't understand why it would be a problem for TDs.
> 
> Intel defined these as reserved. AMD defined them for guest MAXPA. So, yes, OSs
> should be masking them. I'm not suggesting that any are not, but TDX module
> folks were concerned about this, and that then KVM would not be able to turn
> this on later without breaking them. So just circling back here to double check.

I'm with Chao, a kernel/firmware implementation that asserts some CPUID bits that
are currently reserved on _some_ CPUs are always zero deserves to be broken.

  reply	other threads:[~2024-05-07 16:21 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-24 16:55 [RFC] TDX module configurability of 0x80000008 Edgecombe, Rick P
2024-04-25 15:09 ` Xiaoyao Li
2024-04-25 16:31   ` Edgecombe, Rick P
2024-04-25 16:59     ` Sean Christopherson
2024-04-25 18:20       ` Edgecombe, Rick P
2024-04-25 21:39         ` Sean Christopherson
2024-04-25 22:41           ` Edgecombe, Rick P
2024-04-25 22:53             ` Sean Christopherson
2024-04-25 23:08               ` Edgecombe, Rick P
2024-04-25 23:28                 ` Sean Christopherson
2024-04-25 23:38                   ` Edgecombe, Rick P
2024-05-06 18:40                     ` Edgecombe, Rick P
2024-05-07 14:22                       ` Chao Gao
2024-05-07 14:49                         ` Edgecombe, Rick P
2024-05-07 16:21                           ` Sean Christopherson [this message]
2024-05-07 16:41 ` Xiaoyao Li
2024-05-07 17:11   ` Sean Christopherson
2024-05-08  7:50     ` Xiaoyao Li

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