From mboxrd@z Thu Jan 1 00:00:00 1970 From: Deepak Gupta Date: Tue, 14 May 2024 07:38:59 -0700 Subject: [RFC PATCH 5/7] riscv: add double trap driver In-Reply-To: References: <20240418142701.1493091-1-cleger@rivosinc.com> <20240418142701.1493091-6-cleger@rivosinc.com> Message-ID: List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On Tue, May 14, 2024 at 10:06:31AM +0200, Cl?ment L?ger wrote: > > >On 27/04/2024 01:59, Deepak Gupta wrote: >> On Thu, Apr 18, 2024 at 04:26:44PM +0200, Cl?ment L?ger wrote: >>> Add a small driver to request double trap enabling as well as >>> registering a SSE handler for double trap. This will also be used by KVM >>> SBI FWFT extension support to detect if it is possible to enable double >>> trap in VS-mode. >>> >>> Signed-off-by: Cl?ment L?ger >>> --- >>> arch/riscv/include/asm/sbi.h??? |? 1 + >>> drivers/firmware/Kconfig??????? |? 7 +++ >>> drivers/firmware/Makefile?????? |? 1 + >>> drivers/firmware/riscv_dbltrp.c | 95 +++++++++++++++++++++++++++++++++ >>> include/linux/riscv_dbltrp.h??? | 19 +++++++ >>> 5 files changed, 123 insertions(+) >>> create mode 100644 drivers/firmware/riscv_dbltrp.c >>> create mode 100644 include/linux/riscv_dbltrp.h >>> >>> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h >>> index 744aa1796c92..9cd4ca66487c 100644 >>> --- a/arch/riscv/include/asm/sbi.h >>> +++ b/arch/riscv/include/asm/sbi.h >>> @@ -314,6 +314,7 @@ enum sbi_sse_attr_id { >>> #define SBI_SSE_ATTR_INTERRUPTED_FLAGS_SPIE??? (1 << 2) >>> >>> #define SBI_SSE_EVENT_LOCAL_RAS??????? 0x00000000 >>> +#define SBI_SSE_EVENT_LOCAL_DOUBLE_TRAP??? 0x00000001 >>> #define SBI_SSE_EVENT_GLOBAL_RAS??? 0x00008000 >>> #define SBI_SSE_EVENT_LOCAL_PMU??????? 0x00010000 >>> #define SBI_SSE_EVENT_LOCAL_SOFTWARE??? 0xffff0000 >>> diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig >>> index 59f611288807..a037f6e89942 100644 >>> --- a/drivers/firmware/Kconfig >>> +++ b/drivers/firmware/Kconfig >>> @@ -197,6 +197,13 @@ config RISCV_SSE_TEST >>> ????? Select if you want to enable SSE extension testing at boot time. >>> ????? This will run a series of test which verifies SSE sanity. >>> >>> +config RISCV_DBLTRP >>> +??? bool "Enable Double trap handling" >>> +??? depends on RISCV_SSE && RISCV_SBI >>> +??? default n >>> +??? help >>> +????? Select if you want to enable SSE double trap handler. >>> + >>> config SYSFB >>> ????bool >>> ????select BOOT_VESA_SUPPORT >>> diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile >>> index fb7b0c08c56d..ad67a1738c0f 100644 >>> --- a/drivers/firmware/Makefile >>> +++ b/drivers/firmware/Makefile >>> @@ -18,6 +18,7 @@ obj-$(CONFIG_RASPBERRYPI_FIRMWARE) += raspberrypi.o >>> obj-$(CONFIG_FW_CFG_SYSFS)??? += qemu_fw_cfg.o >>> obj-$(CONFIG_RISCV_SSE)??????? += riscv_sse.o >>> obj-$(CONFIG_RISCV_SSE_TEST)??? += riscv_sse_test.o >>> +obj-$(CONFIG_RISCV_DBLTRP)??? += riscv_dbltrp.o >>> obj-$(CONFIG_SYSFB)??????? += sysfb.o >>> obj-$(CONFIG_SYSFB_SIMPLEFB)??? += sysfb_simplefb.o >>> obj-$(CONFIG_TI_SCI_PROTOCOL)??? += ti_sci.o >>> diff --git a/drivers/firmware/riscv_dbltrp.c >>> b/drivers/firmware/riscv_dbltrp.c >>> new file mode 100644 >>> index 000000000000..72f9a067e87a >>> --- /dev/null >>> +++ b/drivers/firmware/riscv_dbltrp.c >>> @@ -0,0 +1,95 @@ >>> +// SPDX-License-Identifier: GPL-2.0-only >>> +/* >>> + * Copyright (C) 2023 Rivos Inc. >>> + */ >> >> nit: fix copyright year >>> + >>> +#define pr_fmt(fmt) "riscv-dbltrp: " fmt >>> + >>> +#include >>> +#include >>> +#include >>> +#include >>> + >>> +#include >>> + >>> +static bool double_trap_enabled; >>> + >>> +static int riscv_sse_dbltrp_handle(uint32_t evt, void *arg, >>> +?????????????????? struct pt_regs *regs) >>> +{ >>> +??? __show_regs(regs); >>> +??? panic("Double trap !\n"); >>> + >>> +??? return 0; >> Curious: >> Does panic return? >> What's the point of returning from here? > >Hi Deepak, > >No, panic() does not return and indeed, the "return 0" is useless. It's >a leftover of a previous implementation without panic in order to keep >GCC mouth shut ;). > >> >>> +} >>> + >>> +struct cpu_dbltrp_data { >>> +??? int error; >>> +}; >>> + >>> +static void >>> +sbi_cpu_enable_double_trap(void *data) >>> +{ >>> +??? struct sbiret ret; >>> +??? struct cpu_dbltrp_data *cdd = data; >>> + >>> +??? ret = sbi_ecall(SBI_EXT_FWFT, SBI_EXT_FWFT_SET, >>> +??????????? SBI_FWFT_DOUBLE_TRAP_ENABLE, 1, 0, 0, 0, 0); >>> + >>> +??? if (ret.error) { >>> +??????? cdd->error = 1; >>> +??????? pr_err("Failed to enable double trap on cpu %d\n", >>> smp_processor_id()); >>> +??? } >>> +} >>> + >>> +static int sbi_enable_double_trap(void) >>> +{ >>> +??? struct cpu_dbltrp_data cdd = {0}; >>> + >>> +??? on_each_cpu(sbi_cpu_enable_double_trap, &cdd, 1); >>> +??? if (cdd.error) >>> +??????? return -1; >> >> There is a bug here. If `sbi_cpu_enable_double_trap` failed on all cpus >> but last cpu. >> Then cdd.error would not record error and will be reflect as if double >> trap was enabled. > >cdd.error is only written in case of error by the per-cpu callbacks, so >it is only set if enabled failed. Is there something I'm missing ? No. Sorry I missed that detail. lgtm. > >Thanks, > >Cl?ment > >> >> Its less likely to happen that FW would return success for one cpu and >> fail for others. >> But there is non-zero probablity here. >> > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0520EC04FFE for ; Tue, 14 May 2024 14:39:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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Tue, 14 May 2024 07:39:01 -0700 (PDT) Date: Tue, 14 May 2024 07:38:59 -0700 From: Deepak Gupta To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Ved Shanbhogue Subject: Re: [RFC PATCH 5/7] riscv: add double trap driver Message-ID: References: <20240418142701.1493091-1-cleger@rivosinc.com> <20240418142701.1493091-6-cleger@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240514_073908_985639_4B030848 X-CRM114-Status: GOOD ( 23.45 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Tue, May 14, 2024 at 10:06:31AM +0200, Cl=E9ment L=E9ger wrote: > > >On 27/04/2024 01:59, Deepak Gupta wrote: >> On Thu, Apr 18, 2024 at 04:26:44PM +0200, Cl=E9ment L=E9ger wrote: >>> Add a small driver to request double trap enabling as well as >>> registering a SSE handler for double trap. This will also be used by KVM >>> SBI FWFT extension support to detect if it is possible to enable double >>> trap in VS-mode. >>> >>> Signed-off-by: Cl=E9ment L=E9ger >>> --- >>> arch/riscv/include/asm/sbi.h=A0=A0=A0 |=A0 1 + >>> drivers/firmware/Kconfig=A0=A0=A0=A0=A0=A0=A0 |=A0 7 +++ >>> drivers/firmware/Makefile=A0=A0=A0=A0=A0=A0 |=A0 1 + >>> drivers/firmware/riscv_dbltrp.c | 95 +++++++++++++++++++++++++++++++++ >>> include/linux/riscv_dbltrp.h=A0=A0=A0 | 19 +++++++ >>> 5 files changed, 123 insertions(+) >>> create mode 100644 drivers/firmware/riscv_dbltrp.c >>> create mode 100644 include/linux/riscv_dbltrp.h >>> >>> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h >>> index 744aa1796c92..9cd4ca66487c 100644 >>> --- a/arch/riscv/include/asm/sbi.h >>> +++ b/arch/riscv/include/asm/sbi.h >>> @@ -314,6 +314,7 @@ enum sbi_sse_attr_id { >>> #define SBI_SSE_ATTR_INTERRUPTED_FLAGS_SPIE=A0=A0=A0 (1 << 2) >>> >>> #define SBI_SSE_EVENT_LOCAL_RAS=A0=A0=A0=A0=A0=A0=A0 0x00000000 >>> +#define SBI_SSE_EVENT_LOCAL_DOUBLE_TRAP=A0=A0=A0 0x00000001 >>> #define SBI_SSE_EVENT_GLOBAL_RAS=A0=A0=A0 0x00008000 >>> #define SBI_SSE_EVENT_LOCAL_PMU=A0=A0=A0=A0=A0=A0=A0 0x00010000 >>> #define SBI_SSE_EVENT_LOCAL_SOFTWARE=A0=A0=A0 0xffff0000 >>> diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig >>> index 59f611288807..a037f6e89942 100644 >>> --- a/drivers/firmware/Kconfig >>> +++ b/drivers/firmware/Kconfig >>> @@ -197,6 +197,13 @@ config RISCV_SSE_TEST >>> =A0=A0=A0=A0=A0 Select if you want to enable SSE extension testing at b= oot time. >>> =A0=A0=A0=A0=A0 This will run a series of test which verifies SSE sanit= y. >>> >>> +config RISCV_DBLTRP >>> +=A0=A0=A0 bool "Enable Double trap handling" >>> +=A0=A0=A0 depends on RISCV_SSE && RISCV_SBI >>> +=A0=A0=A0 default n >>> +=A0=A0=A0 help >>> +=A0=A0=A0=A0=A0 Select if you want to enable SSE double trap handler. >>> + >>> config SYSFB >>> =A0=A0=A0=A0bool >>> =A0=A0=A0=A0select BOOT_VESA_SUPPORT >>> diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile >>> index fb7b0c08c56d..ad67a1738c0f 100644 >>> --- a/drivers/firmware/Makefile >>> +++ b/drivers/firmware/Makefile >>> @@ -18,6 +18,7 @@ obj-$(CONFIG_RASPBERRYPI_FIRMWARE) +=3D raspberrypi.o >>> obj-$(CONFIG_FW_CFG_SYSFS)=A0=A0=A0 +=3D qemu_fw_cfg.o >>> obj-$(CONFIG_RISCV_SSE)=A0=A0=A0=A0=A0=A0=A0 +=3D riscv_sse.o >>> obj-$(CONFIG_RISCV_SSE_TEST)=A0=A0=A0 +=3D riscv_sse_test.o >>> +obj-$(CONFIG_RISCV_DBLTRP)=A0=A0=A0 +=3D riscv_dbltrp.o >>> obj-$(CONFIG_SYSFB)=A0=A0=A0=A0=A0=A0=A0 +=3D sysfb.o >>> obj-$(CONFIG_SYSFB_SIMPLEFB)=A0=A0=A0 +=3D sysfb_simplefb.o >>> obj-$(CONFIG_TI_SCI_PROTOCOL)=A0=A0=A0 +=3D ti_sci.o >>> diff --git a/drivers/firmware/riscv_dbltrp.c >>> b/drivers/firmware/riscv_dbltrp.c >>> new file mode 100644 >>> index 000000000000..72f9a067e87a >>> --- /dev/null >>> +++ b/drivers/firmware/riscv_dbltrp.c >>> @@ -0,0 +1,95 @@ >>> +// SPDX-License-Identifier: GPL-2.0-only >>> +/* >>> + * Copyright (C) 2023 Rivos Inc. >>> + */ >> >> nit: fix copyright year >>> + >>> +#define pr_fmt(fmt) "riscv-dbltrp: " fmt >>> + >>> +#include >>> +#include >>> +#include >>> +#include >>> + >>> +#include >>> + >>> +static bool double_trap_enabled; >>> + >>> +static int riscv_sse_dbltrp_handle(uint32_t evt, void *arg, >>> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 struct pt_regs = *regs) >>> +{ >>> +=A0=A0=A0 __show_regs(regs); >>> +=A0=A0=A0 panic("Double trap !\n"); >>> + >>> +=A0=A0=A0 return 0; >> Curious: >> Does panic return? >> What's the point of returning from here? > >Hi Deepak, > >No, panic() does not return and indeed, the "return 0" is useless. It's >a leftover of a previous implementation without panic in order to keep >GCC mouth shut ;). > >> >>> +} >>> + >>> +struct cpu_dbltrp_data { >>> +=A0=A0=A0 int error; >>> +}; >>> + >>> +static void >>> +sbi_cpu_enable_double_trap(void *data) >>> +{ >>> +=A0=A0=A0 struct sbiret ret; >>> +=A0=A0=A0 struct cpu_dbltrp_data *cdd =3D data; >>> + >>> +=A0=A0=A0 ret =3D sbi_ecall(SBI_EXT_FWFT, SBI_EXT_FWFT_SET, >>> +=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 SBI_FWFT_DOUBLE_TRAP_ENABLE, 1, 0, 0= , 0, 0); >>> + >>> +=A0=A0=A0 if (ret.error) { >>> +=A0=A0=A0=A0=A0=A0=A0 cdd->error =3D 1; >>> +=A0=A0=A0=A0=A0=A0=A0 pr_err("Failed to enable double trap on cpu %d\n= ", >>> smp_processor_id()); >>> +=A0=A0=A0 } >>> +} >>> + >>> +static int sbi_enable_double_trap(void) >>> +{ >>> +=A0=A0=A0 struct cpu_dbltrp_data cdd =3D {0}; >>> + >>> +=A0=A0=A0 on_each_cpu(sbi_cpu_enable_double_trap, &cdd, 1); >>> +=A0=A0=A0 if (cdd.error) >>> +=A0=A0=A0=A0=A0=A0=A0 return -1; >> >> There is a bug here. If `sbi_cpu_enable_double_trap` failed on all cpus >> but last cpu. >> Then cdd.error would not record error and will be reflect as if double >> trap was enabled. > >cdd.error is only written in case of error by the per-cpu callbacks, so >it is only set if enabled failed. Is there something I'm missing ? No. Sorry I missed that detail. lgtm. > >Thanks, > >Cl=E9ment > >> >> Its less likely to happen that FW would return success for one cpu and >> fail for others. >> But there is non-zero probablity here. >> > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f179.google.com (mail-pf1-f179.google.com [209.85.210.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AE65144D01 for ; Tue, 14 May 2024 14:39:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.179 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715697544; cv=none; b=deBIDsz5Nre+mngA9h27aa/MFZ9dhGQLToBjUczZKgliWQuRf44VTOz+3qmTscDFN+6Q0IB7y4zuY81vf9dvaH2Q+4ANLUdq7IfNlPXnSQPofswKudGWzrK7jspdGzhQz0jHsshtPqg54xzcYc1tYgpG9L3CVuRbfkdqUdl6NEU= ARC-Message-Signature:i=1; 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Tue, 14 May 2024 07:39:01 -0700 (PDT) Date: Tue, 14 May 2024 07:38:59 -0700 From: Deepak Gupta To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Atish Patra , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Ved Shanbhogue Subject: Re: [RFC PATCH 5/7] riscv: add double trap driver Message-ID: References: <20240418142701.1493091-1-cleger@rivosinc.com> <20240418142701.1493091-6-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Tue, May 14, 2024 at 10:06:31AM +0200, Clément Léger wrote: > > >On 27/04/2024 01:59, Deepak Gupta wrote: >> On Thu, Apr 18, 2024 at 04:26:44PM +0200, Clément Léger wrote: >>> Add a small driver to request double trap enabling as well as >>> registering a SSE handler for double trap. This will also be used by KVM >>> SBI FWFT extension support to detect if it is possible to enable double >>> trap in VS-mode. >>> >>> Signed-off-by: Clément Léger >>> --- >>> arch/riscv/include/asm/sbi.h    |  1 + >>> drivers/firmware/Kconfig        |  7 +++ >>> drivers/firmware/Makefile       |  1 + >>> drivers/firmware/riscv_dbltrp.c | 95 +++++++++++++++++++++++++++++++++ >>> include/linux/riscv_dbltrp.h    | 19 +++++++ >>> 5 files changed, 123 insertions(+) >>> create mode 100644 drivers/firmware/riscv_dbltrp.c >>> create mode 100644 include/linux/riscv_dbltrp.h >>> >>> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h >>> index 744aa1796c92..9cd4ca66487c 100644 >>> --- a/arch/riscv/include/asm/sbi.h >>> +++ b/arch/riscv/include/asm/sbi.h >>> @@ -314,6 +314,7 @@ enum sbi_sse_attr_id { >>> #define SBI_SSE_ATTR_INTERRUPTED_FLAGS_SPIE    (1 << 2) >>> >>> #define SBI_SSE_EVENT_LOCAL_RAS        0x00000000 >>> +#define SBI_SSE_EVENT_LOCAL_DOUBLE_TRAP    0x00000001 >>> #define SBI_SSE_EVENT_GLOBAL_RAS    0x00008000 >>> #define SBI_SSE_EVENT_LOCAL_PMU        0x00010000 >>> #define SBI_SSE_EVENT_LOCAL_SOFTWARE    0xffff0000 >>> diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig >>> index 59f611288807..a037f6e89942 100644 >>> --- a/drivers/firmware/Kconfig >>> +++ b/drivers/firmware/Kconfig >>> @@ -197,6 +197,13 @@ config RISCV_SSE_TEST >>>       Select if you want to enable SSE extension testing at boot time. >>>       This will run a series of test which verifies SSE sanity. >>> >>> +config RISCV_DBLTRP >>> +    bool "Enable Double trap handling" >>> +    depends on RISCV_SSE && RISCV_SBI >>> +    default n >>> +    help >>> +      Select if you want to enable SSE double trap handler. >>> + >>> config SYSFB >>>     bool >>>     select BOOT_VESA_SUPPORT >>> diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile >>> index fb7b0c08c56d..ad67a1738c0f 100644 >>> --- a/drivers/firmware/Makefile >>> +++ b/drivers/firmware/Makefile >>> @@ -18,6 +18,7 @@ obj-$(CONFIG_RASPBERRYPI_FIRMWARE) += raspberrypi.o >>> obj-$(CONFIG_FW_CFG_SYSFS)    += qemu_fw_cfg.o >>> obj-$(CONFIG_RISCV_SSE)        += riscv_sse.o >>> obj-$(CONFIG_RISCV_SSE_TEST)    += riscv_sse_test.o >>> +obj-$(CONFIG_RISCV_DBLTRP)    += riscv_dbltrp.o >>> obj-$(CONFIG_SYSFB)        += sysfb.o >>> obj-$(CONFIG_SYSFB_SIMPLEFB)    += sysfb_simplefb.o >>> obj-$(CONFIG_TI_SCI_PROTOCOL)    += ti_sci.o >>> diff --git a/drivers/firmware/riscv_dbltrp.c >>> b/drivers/firmware/riscv_dbltrp.c >>> new file mode 100644 >>> index 000000000000..72f9a067e87a >>> --- /dev/null >>> +++ b/drivers/firmware/riscv_dbltrp.c >>> @@ -0,0 +1,95 @@ >>> +// SPDX-License-Identifier: GPL-2.0-only >>> +/* >>> + * Copyright (C) 2023 Rivos Inc. >>> + */ >> >> nit: fix copyright year >>> + >>> +#define pr_fmt(fmt) "riscv-dbltrp: " fmt >>> + >>> +#include >>> +#include >>> +#include >>> +#include >>> + >>> +#include >>> + >>> +static bool double_trap_enabled; >>> + >>> +static int riscv_sse_dbltrp_handle(uint32_t evt, void *arg, >>> +                   struct pt_regs *regs) >>> +{ >>> +    __show_regs(regs); >>> +    panic("Double trap !\n"); >>> + >>> +    return 0; >> Curious: >> Does panic return? >> What's the point of returning from here? > >Hi Deepak, > >No, panic() does not return and indeed, the "return 0" is useless. It's >a leftover of a previous implementation without panic in order to keep >GCC mouth shut ;). > >> >>> +} >>> + >>> +struct cpu_dbltrp_data { >>> +    int error; >>> +}; >>> + >>> +static void >>> +sbi_cpu_enable_double_trap(void *data) >>> +{ >>> +    struct sbiret ret; >>> +    struct cpu_dbltrp_data *cdd = data; >>> + >>> +    ret = sbi_ecall(SBI_EXT_FWFT, SBI_EXT_FWFT_SET, >>> +            SBI_FWFT_DOUBLE_TRAP_ENABLE, 1, 0, 0, 0, 0); >>> + >>> +    if (ret.error) { >>> +        cdd->error = 1; >>> +        pr_err("Failed to enable double trap on cpu %d\n", >>> smp_processor_id()); >>> +    } >>> +} >>> + >>> +static int sbi_enable_double_trap(void) >>> +{ >>> +    struct cpu_dbltrp_data cdd = {0}; >>> + >>> +    on_each_cpu(sbi_cpu_enable_double_trap, &cdd, 1); >>> +    if (cdd.error) >>> +        return -1; >> >> There is a bug here. If `sbi_cpu_enable_double_trap` failed on all cpus >> but last cpu. >> Then cdd.error would not record error and will be reflect as if double >> trap was enabled. > >cdd.error is only written in case of error by the per-cpu callbacks, so >it is only set if enabled failed. Is there something I'm missing ? No. Sorry I missed that detail. lgtm. > >Thanks, > >Clément > >> >> Its less likely to happen that FW would return success for one cpu and >> fail for others. >> But there is non-zero probablity here. >> >