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Thu, 30 May 2024 04:54:47 -0700 (PDT) Received: from andrea ([151.76.32.59]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-578f47126f0sm7346919a12.91.2024.05.30.04.54.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 04:54:47 -0700 (PDT) Date: Thu, 30 May 2024 13:54:43 +0200 From: Andrea Parri To: Alexandre Ghiti Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Leonardo Bras , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH -fixes] riscv: Fix fully ordered LR/SC xchg[8|16]() implementations Message-ID: References: <20240530075424.380557-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240530075424.380557-1-alexghiti@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240530_045451_931128_E93B967E X-CRM114-Status: GOOD ( 10.00 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org > -#define _arch_xchg(ptr, new, sfx, prepend, append) \ > +#define _arch_xchg(ptr, new, sc_sfx, swap_sfx, prepend, append) \ > ({ \ > __typeof__(ptr) __ptr = (ptr); \ > __typeof__(*(__ptr)) __new = (new); \ > @@ -55,15 +55,15 @@ > switch (sizeof(*__ptr)) { \ > case 1: \ > case 2: \ > - __arch_xchg_masked(prepend, append, \ > + __arch_xchg_masked(sc_sfx, prepend, append, \ > __ret, __ptr, __new); \ > break; \ > case 4: \ > - __arch_xchg(".w" sfx, prepend, append, \ > + __arch_xchg(".w" swap_sfx, prepend, append, \ > __ret, __ptr, __new); \ > break; \ > case 8: \ > - __arch_xchg(".d" sfx, prepend, append, \ > + __arch_xchg(".d" swap_sfx, prepend, append, \ > __ret, __ptr, __new); \ > break; \ > default: \ > @@ -73,16 +73,16 @@ > }) > > #define arch_xchg_relaxed(ptr, x) \ > - _arch_xchg(ptr, x, "", "", "") > + _arch_xchg(ptr, x, "", "", "", "") > > #define arch_xchg_acquire(ptr, x) \ > - _arch_xchg(ptr, x, "", "", RISCV_ACQUIRE_BARRIER) > + _arch_xchg(ptr, x, "", "", "", RISCV_ACQUIRE_BARRIER) > > #define arch_xchg_release(ptr, x) \ > - _arch_xchg(ptr, x, "", RISCV_RELEASE_BARRIER, "") > + _arch_xchg(ptr, x, "", "", RISCV_RELEASE_BARRIER, "") > > #define arch_xchg(ptr, x) \ > - _arch_xchg(ptr, x, ".aqrl", "", "") > + _arch_xchg(ptr, x, ".rl", ".aqrl", "", " fence rw, rw\n") This does indeed fix the fully-ordered variant of xchg8/16(). But this also changes the fully-ordered xchg32() to amoswap.w.aqrl a4,a5,(s1) fence rw,rw (and similarly for xchg64()); we should be able to restore the original mapping with the diff below on top of this patch. Andrea P.S. Perhaps expand the width of the macros to avoid newlines (I didn't do it keep the diff smaller). P.S. With Zabha, we'd probably like to pass swap_sfx and swap_append as well to __arch_xchg_masked(). diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index e1e564f5dc7ba..88c8bb7ec1c34 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -46,7 +46,8 @@ : "memory"); \ }) -#define _arch_xchg(ptr, new, sc_sfx, swap_sfx, prepend, append) \ +#define _arch_xchg(ptr, new, sc_sfx, swap_sfx, prepend, \ + sc_append, swap_append) \ ({ \ __typeof__(ptr) __ptr = (ptr); \ __typeof__(*(__ptr)) __new = (new); \ @@ -55,15 +56,15 @@ switch (sizeof(*__ptr)) { \ case 1: \ case 2: \ - __arch_xchg_masked(sc_sfx, prepend, append, \ + __arch_xchg_masked(sc_sfx, prepend, sc_append, \ __ret, __ptr, __new); \ break; \ case 4: \ - __arch_xchg(".w" swap_sfx, prepend, append, \ + __arch_xchg(".w" swap_sfx, prepend, swap_append, \ __ret, __ptr, __new); \ break; \ case 8: \ - __arch_xchg(".d" swap_sfx, prepend, append, \ + __arch_xchg(".d" swap_sfx, prepend, swap_append, \ __ret, __ptr, __new); \ break; \ default: \ @@ -73,16 +74,16 @@ }) #define arch_xchg_relaxed(ptr, x) \ - _arch_xchg(ptr, x, "", "", "", "") + _arch_xchg(ptr, x, "", "", "", "", "") #define arch_xchg_acquire(ptr, x) \ - _arch_xchg(ptr, x, "", "", "", RISCV_ACQUIRE_BARRIER) + _arch_xchg(ptr, x, "", "", "", RISCV_ACQUIRE_BARRIER, RISCV_ACQUIRE_BARRIER) #define arch_xchg_release(ptr, x) \ - _arch_xchg(ptr, x, "", "", RISCV_RELEASE_BARRIER, "") + _arch_xchg(ptr, x, "", "", RISCV_RELEASE_BARRIER, "", "") #define arch_xchg(ptr, x) \ - _arch_xchg(ptr, x, ".rl", ".aqrl", "", " fence rw, rw\n") + _arch_xchg(ptr, x, ".rl", ".aqrl", "", " fence rw, rw\n", "") #define xchg32(ptr, x) \ ({ \ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A142417C7A3 for ; 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Thu, 30 May 2024 04:54:47 -0700 (PDT) Received: from andrea ([151.76.32.59]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-578f47126f0sm7346919a12.91.2024.05.30.04.54.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 May 2024 04:54:47 -0700 (PDT) Date: Thu, 30 May 2024 13:54:43 +0200 From: Andrea Parri To: Alexandre Ghiti Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Leonardo Bras , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH -fixes] riscv: Fix fully ordered LR/SC xchg[8|16]() implementations Message-ID: References: <20240530075424.380557-1-alexghiti@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240530075424.380557-1-alexghiti@rivosinc.com> > -#define _arch_xchg(ptr, new, sfx, prepend, append) \ > +#define _arch_xchg(ptr, new, sc_sfx, swap_sfx, prepend, append) \ > ({ \ > __typeof__(ptr) __ptr = (ptr); \ > __typeof__(*(__ptr)) __new = (new); \ > @@ -55,15 +55,15 @@ > switch (sizeof(*__ptr)) { \ > case 1: \ > case 2: \ > - __arch_xchg_masked(prepend, append, \ > + __arch_xchg_masked(sc_sfx, prepend, append, \ > __ret, __ptr, __new); \ > break; \ > case 4: \ > - __arch_xchg(".w" sfx, prepend, append, \ > + __arch_xchg(".w" swap_sfx, prepend, append, \ > __ret, __ptr, __new); \ > break; \ > case 8: \ > - __arch_xchg(".d" sfx, prepend, append, \ > + __arch_xchg(".d" swap_sfx, prepend, append, \ > __ret, __ptr, __new); \ > break; \ > default: \ > @@ -73,16 +73,16 @@ > }) > > #define arch_xchg_relaxed(ptr, x) \ > - _arch_xchg(ptr, x, "", "", "") > + _arch_xchg(ptr, x, "", "", "", "") > > #define arch_xchg_acquire(ptr, x) \ > - _arch_xchg(ptr, x, "", "", RISCV_ACQUIRE_BARRIER) > + _arch_xchg(ptr, x, "", "", "", RISCV_ACQUIRE_BARRIER) > > #define arch_xchg_release(ptr, x) \ > - _arch_xchg(ptr, x, "", RISCV_RELEASE_BARRIER, "") > + _arch_xchg(ptr, x, "", "", RISCV_RELEASE_BARRIER, "") > > #define arch_xchg(ptr, x) \ > - _arch_xchg(ptr, x, ".aqrl", "", "") > + _arch_xchg(ptr, x, ".rl", ".aqrl", "", " fence rw, rw\n") This does indeed fix the fully-ordered variant of xchg8/16(). But this also changes the fully-ordered xchg32() to amoswap.w.aqrl a4,a5,(s1) fence rw,rw (and similarly for xchg64()); we should be able to restore the original mapping with the diff below on top of this patch. Andrea P.S. Perhaps expand the width of the macros to avoid newlines (I didn't do it keep the diff smaller). P.S. With Zabha, we'd probably like to pass swap_sfx and swap_append as well to __arch_xchg_masked(). diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h index e1e564f5dc7ba..88c8bb7ec1c34 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -46,7 +46,8 @@ : "memory"); \ }) -#define _arch_xchg(ptr, new, sc_sfx, swap_sfx, prepend, append) \ +#define _arch_xchg(ptr, new, sc_sfx, swap_sfx, prepend, \ + sc_append, swap_append) \ ({ \ __typeof__(ptr) __ptr = (ptr); \ __typeof__(*(__ptr)) __new = (new); \ @@ -55,15 +56,15 @@ switch (sizeof(*__ptr)) { \ case 1: \ case 2: \ - __arch_xchg_masked(sc_sfx, prepend, append, \ + __arch_xchg_masked(sc_sfx, prepend, sc_append, \ __ret, __ptr, __new); \ break; \ case 4: \ - __arch_xchg(".w" swap_sfx, prepend, append, \ + __arch_xchg(".w" swap_sfx, prepend, swap_append, \ __ret, __ptr, __new); \ break; \ case 8: \ - __arch_xchg(".d" swap_sfx, prepend, append, \ + __arch_xchg(".d" swap_sfx, prepend, swap_append, \ __ret, __ptr, __new); \ break; \ default: \ @@ -73,16 +74,16 @@ }) #define arch_xchg_relaxed(ptr, x) \ - _arch_xchg(ptr, x, "", "", "", "") + _arch_xchg(ptr, x, "", "", "", "", "") #define arch_xchg_acquire(ptr, x) \ - _arch_xchg(ptr, x, "", "", "", RISCV_ACQUIRE_BARRIER) + _arch_xchg(ptr, x, "", "", "", RISCV_ACQUIRE_BARRIER, RISCV_ACQUIRE_BARRIER) #define arch_xchg_release(ptr, x) \ - _arch_xchg(ptr, x, "", "", RISCV_RELEASE_BARRIER, "") + _arch_xchg(ptr, x, "", "", RISCV_RELEASE_BARRIER, "", "") #define arch_xchg(ptr, x) \ - _arch_xchg(ptr, x, ".rl", ".aqrl", "", " fence rw, rw\n") + _arch_xchg(ptr, x, ".rl", ".aqrl", "", " fence rw, rw\n", "") #define xchg32(ptr, x) \ ({ \