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Fri, 31 May 2024 08:52:14 -0700 (PDT) Received: from andrea ([151.76.32.59]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57a31b98e01sm1135963a12.16.2024.05.31.08.52.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 May 2024 08:52:14 -0700 (PDT) Date: Fri, 31 May 2024 17:52:09 +0200 From: Andrea Parri To: Alexandre Ghiti Cc: Alexandre Ghiti , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Ingo Molnar , Will Deacon , Waiman Long , Boqun Feng , Arnd Bergmann , Leonardo Bras , Guo Ren , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org Subject: Re: [PATCH 7/7] riscv: Add qspinlock support based on Zabha extension Message-ID: References: <20240528151052.313031-1-alexghiti@rivosinc.com> <20240528151052.313031-8-alexghiti@rivosinc.com> <39a9b28c-2792-45ce-a8c6-1703cab0f2de@ghiti.fr> Precedence: bulk X-Mailing-List: linux-arch@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <39a9b28c-2792-45ce-a8c6-1703cab0f2de@ghiti.fr> > > > + select ARCH_USE_QUEUED_SPINLOCKS if TOOLCHAIN_HAS_ZABHA > > IIUC, we should make sure qspinlocks run with ARCH_WEAK_RELEASE_ACQUIRE, > > perhaps a similar select for the latter? (not a kconfig expert) > > > Where did you see this dependency? And if that is really a dependency of > qspinlocks, shouldn't this be under CONFIG_QUEUED_SPINLOCKS? (not a Kconfig > expert too). The comment on smp_mb__after_unlock_lock() in include/linux/rcupdate.h (the barrier is currently only used by the RCU subsystem) recalls: /* * Place this after a lock-acquisition primitive to guarantee that * an UNLOCK+LOCK pair acts as a full barrier. This guarantee applies * if the UNLOCK and LOCK are executed by the same CPU or if the * UNLOCK and LOCK operate on the same lock variable. */ #ifdef CONFIG_ARCH_WEAK_RELEASE_ACQUIRE #define smp_mb__after_unlock_lock() smp_mb() /* Full ordering for lock. */ #else /* #ifdef CONFIG_ARCH_WEAK_RELEASE_ACQUIRE */ #define smp_mb__after_unlock_lock() do { } while (0) #endif /* #else #ifdef CONFIG_ARCH_WEAK_RELEASE_ACQUIRE */ Architectures whose UNLOCK+LOCK implementation does not (already) meet the required "full barrier" ordering property (currently, only powerpc) can overwrite the "default"/common #define for this barrier (NOP) and meet the ordering by opting in for ARCH_WEAK_RELEASE_ACQUIRE. The (current) "generic" ticket lock implementation provides "the full barrier" in its LOCK operations (hence in part. in UNLOCK+LOCK), cf. arch_spin_trylock() -> atomic_try_cmpxchg() arch_spin_lock() -> atomic_fetch_add() -> atomic_cond_read_acquire(); smp_mb() but the "UNLOCK+LOCK pairs act as a full barrier" property doesn't hold true for riscv (and powerpc) when switching over to queued spinlocks. OTOH, I see no particular reason for other "users" of queued spinlocks (notably, x86 and arm64) for selecting ARCH_WEAK_RELEASE_ACQUIRE. But does this address your concern? Let me know if I misunderstood it. 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Fri, 31 May 2024 08:52:14 -0700 (PDT) Received: from andrea ([151.76.32.59]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57a31b98e01sm1135963a12.16.2024.05.31.08.52.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 May 2024 08:52:14 -0700 (PDT) Date: Fri, 31 May 2024 17:52:09 +0200 From: Andrea Parri To: Alexandre Ghiti Cc: Alexandre Ghiti , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Peter Zijlstra , Ingo Molnar , Will Deacon , Waiman Long , Boqun Feng , Arnd Bergmann , Leonardo Bras , Guo Ren , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org Subject: Re: [PATCH 7/7] riscv: Add qspinlock support based on Zabha extension Message-ID: References: <20240528151052.313031-1-alexghiti@rivosinc.com> <20240528151052.313031-8-alexghiti@rivosinc.com> <39a9b28c-2792-45ce-a8c6-1703cab0f2de@ghiti.fr> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <39a9b28c-2792-45ce-a8c6-1703cab0f2de@ghiti.fr> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240531_085220_872851_3F8F5184 X-CRM114-Status: GOOD ( 14.68 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org > > > + select ARCH_USE_QUEUED_SPINLOCKS if TOOLCHAIN_HAS_ZABHA > > IIUC, we should make sure qspinlocks run with ARCH_WEAK_RELEASE_ACQUIRE, > > perhaps a similar select for the latter? (not a kconfig expert) > > > Where did you see this dependency? And if that is really a dependency of > qspinlocks, shouldn't this be under CONFIG_QUEUED_SPINLOCKS? (not a Kconfig > expert too). The comment on smp_mb__after_unlock_lock() in include/linux/rcupdate.h (the barrier is currently only used by the RCU subsystem) recalls: /* * Place this after a lock-acquisition primitive to guarantee that * an UNLOCK+LOCK pair acts as a full barrier. This guarantee applies * if the UNLOCK and LOCK are executed by the same CPU or if the * UNLOCK and LOCK operate on the same lock variable. */ #ifdef CONFIG_ARCH_WEAK_RELEASE_ACQUIRE #define smp_mb__after_unlock_lock() smp_mb() /* Full ordering for lock. */ #else /* #ifdef CONFIG_ARCH_WEAK_RELEASE_ACQUIRE */ #define smp_mb__after_unlock_lock() do { } while (0) #endif /* #else #ifdef CONFIG_ARCH_WEAK_RELEASE_ACQUIRE */ Architectures whose UNLOCK+LOCK implementation does not (already) meet the required "full barrier" ordering property (currently, only powerpc) can overwrite the "default"/common #define for this barrier (NOP) and meet the ordering by opting in for ARCH_WEAK_RELEASE_ACQUIRE. The (current) "generic" ticket lock implementation provides "the full barrier" in its LOCK operations (hence in part. in UNLOCK+LOCK), cf. arch_spin_trylock() -> atomic_try_cmpxchg() arch_spin_lock() -> atomic_fetch_add() -> atomic_cond_read_acquire(); smp_mb() but the "UNLOCK+LOCK pairs act as a full barrier" property doesn't hold true for riscv (and powerpc) when switching over to queued spinlocks. OTOH, I see no particular reason for other "users" of queued spinlocks (notably, x86 and arm64) for selecting ARCH_WEAK_RELEASE_ACQUIRE. But does this address your concern? Let me know if I misunderstood it. Andrea _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv