Re: [PATCH 1/1] arm64: dts: imx8dxl-evk: add imx8dxl_cm4, lsio mu5, related memory region

[Shawn Guo <shawnguo2@yeah.net>]

On Wed, Jun 05, 2024 at 04:27:03PM -0400, Frank Li wrote:
> Add imx8dxl_cm4, lsio mu5 and related memory region.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 48 +++++++++++++++++++
>  1 file changed, 48 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
> index 4ac96a0586294..c5e601b98cf8f 100644
> --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
> @@ -24,6 +24,19 @@ chosen {
>  		stdout-path = &lpuart0;
>  	};
>  
> +	imx8dxl-cm4 {
> +		compatible = "fsl,imx8qxp-cm4";
> +		clocks = <&clk_dummy>;
> +		mbox-names = "tx", "rx", "rxdb";
> +		mboxes = <&lsio_mu5 0 1 &lsio_mu5 1 1 &lsio_mu5 3 1>;
> +		memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
> +				<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
> +		power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>;
> +		fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
> +		fsl,entry-address = <0x34fe0000>;
> +	};
> +
> +
>  	memory@80000000 {
>  		device_type = "memory";
>  		reg = <0x00000000 0x80000000 0 0x40000000>;
> @@ -51,6 +64,37 @@ linux,cma {
>  			alloc-ranges = <0 0x98000000 0 0x14000000>;
>  			linux,cma-default;
>  		};
> +
> +		vdev0vring0: memory0@90000000 {
> +			reg = <0 0x90000000 0 0x8000>;
> +			no-map;
> +		};
> +
> +		vdev0vring1: memory@90008000 {
> +			reg = <0 0x90008000 0 0x8000>;
> +			no-map;
> +		};
> +
> +		vdev1vring0: memory@90010000 {
> +			reg = <0 0x90010000 0 0x8000>;
> +			no-map;
> +		};
> +
> +		vdev1vring1: memory@90018000 {
> +			reg = <0 0x90018000 0 0x8000>;
> +			no-map;
> +		};
> +
> +		rsc_table: memory-rsc-table@900ff000 {
> +			reg = <0 0x900ff000 0 0x1000>;
> +			no-map;
> +		};
> +
> +		vdevbuffer: memory-vdevbuffer {

As kernel test robot reported, unit-address is missing here?

Shawn

> +			compatible = "shared-dma-pool";
> +			reg = <0 0x90400000 0 0x100000>;
> +			no-map;
> +		};
>  	};
>  
>  	m2_uart1_sel: regulator-m2uart1sel {
> @@ -505,6 +549,10 @@ &lpuart1 {
>  	status = "okay";
>  };
>  
> +&lsio_mu5 {
> +	status = "okay";
> +};
> +
>  &flexcan2 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_flexcan2>;
> -- 
> 2.34.1
>