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[35.190.215.205]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-422f602feb0sm158291435e9.20.2024.06.17.07.55.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Jun 2024 07:55:34 -0700 (PDT) Date: Mon, 17 Jun 2024 14:55:30 +0000 From: Mostafa Saleh To: Eric Auger Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org, qemu-devel@nongnu.org, jean-philippe@linaro.org, alex.bennee@linaro.org, maz@kernel.org, nicolinc@nvidia.com, julien@xen.org, richard.henderson@linaro.org, marcin.juszkiewicz@linaro.org Subject: Re: [RFC PATCH v3 06/18] hw/arm/smmu: Consolidate ASID and VMID types Message-ID: References: <20240429032403.74910-1-smostafa@google.com> <20240429032403.74910-7-smostafa@google.com> <195e906c-d263-4736-91aa-69274fa85180@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <195e906c-d263-4736-91aa-69274fa85180@redhat.com> X-TUID: DR4ECBOs3ZQr Hi Eric, Sorry no updates for a while, I have been away for some time, but I am now back to working on this. On Wed, May 15, 2024 at 02:41:42PM +0200, Eric Auger wrote: > Hi Mostafa, > On 4/29/24 05:23, Mostafa Saleh wrote: > > ASID and VMID used to be uint16_t in the translation config, however, > > in other contexts they can be int as -1 in case of TLB invalidation, > other contexts = TLB invalidation, right? Yes, although I was thinking this can be used for global entries lookup also in case we would support it in the future. Thanks, Mostafa > > to represent all(don’t care). > add space bewteen all and (. > > When stage-2 was added asid was set to -1 in stage-2 and vmid to -1 > > in stage-1 configs. However, that meant they were set as (65536), > > this was not an issue as nesting was not supported and no > > commands/lookup targets both. > s/targets/uses > > > > With nesting, it’s critical to get this right as translation must be > > tagged correctly with ASID/VMID, and with ASID=-1 meaning stage-2. > > Represent ASID/VMID everywhere as int. > > > > Signed-off-by: Mostafa Saleh > > --- > > hw/arm/smmu-common.c | 10 +++++----- > > hw/arm/smmuv3.c | 4 ++-- > > hw/arm/trace-events | 18 +++++++++--------- > > include/hw/arm/smmu-common.h | 14 +++++++------- > > 4 files changed, 23 insertions(+), 23 deletions(-) > > > > diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c > > index d94db6b34f..21982621c0 100644 > > --- a/hw/arm/smmu-common.c > > +++ b/hw/arm/smmu-common.c > > @@ -57,7 +57,7 @@ static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2) > > (k1->vmid == k2->vmid); > > } > > > > -SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iova, > > +SMMUIOTLBKey smmu_get_iotlb_key(int asid, int vmid, uint64_t iova, > > uint8_t tg, uint8_t level) > > { > > SMMUIOTLBKey key = {.asid = asid, .vmid = vmid, .iova = iova, > > @@ -130,7 +130,7 @@ void smmu_iotlb_inv_all(SMMUState *s) > > static gboolean smmu_hash_remove_by_asid(gpointer key, gpointer value, > > gpointer user_data) > > { > > - uint16_t asid = *(uint16_t *)user_data; > > + int asid = *(int *)user_data; > > SMMUIOTLBKey *iotlb_key = (SMMUIOTLBKey *)key; > > > > return SMMU_IOTLB_ASID(*iotlb_key) == asid; > > @@ -139,7 +139,7 @@ static gboolean smmu_hash_remove_by_asid(gpointer key, gpointer value, > > static gboolean smmu_hash_remove_by_vmid(gpointer key, gpointer value, > > gpointer user_data) > > { > > - uint16_t vmid = *(uint16_t *)user_data; > > + int vmid = *(int *)user_data; > > SMMUIOTLBKey *iotlb_key = (SMMUIOTLBKey *)key; > > > > return SMMU_IOTLB_VMID(*iotlb_key) == vmid; > > @@ -191,13 +191,13 @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, > > &info); > > } > > > > -void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid) > > +void smmu_iotlb_inv_asid(SMMUState *s, int asid) > > { > > trace_smmu_iotlb_inv_asid(asid); > > g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid); > > } > > > > -void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid) > > +void smmu_iotlb_inv_vmid(SMMUState *s, int vmid) > > { > > trace_smmu_iotlb_inv_vmid(vmid); > > g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_vmid, &vmid); > > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > > index f98c157221..cc61708160 100644 > > --- a/hw/arm/smmuv3.c > > +++ b/hw/arm/smmuv3.c > > @@ -1243,7 +1243,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) > > } > > case SMMU_CMD_TLBI_NH_ASID: > > { > > - uint16_t asid = CMD_ASID(&cmd); > > + int asid = CMD_ASID(&cmd); > > > > if (!STAGE1_SUPPORTED(s)) { > > cmd_error = SMMU_CERROR_ILL; > > @@ -1276,7 +1276,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) > > break; > > case SMMU_CMD_TLBI_S12_VMALL: > > { > > - uint16_t vmid = CMD_VMID(&cmd); > > + int vmid = CMD_VMID(&cmd); > > > > if (!STAGE2_SUPPORTED(s)) { > > cmd_error = SMMU_CERROR_ILL; > > diff --git a/hw/arm/trace-events b/hw/arm/trace-events > > index cc12924a84..09ccd39548 100644 > > --- a/hw/arm/trace-events > > +++ b/hw/arm/trace-events > > @@ -11,13 +11,13 @@ smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint6 > > smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" iova=0x%"PRIx64" block address = 0x%"PRIx64" block size = %d MiB" > > smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64 > > smmu_iotlb_inv_all(void) "IOTLB invalidate all" > > -smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=%d" > > -smmu_iotlb_inv_vmid(uint16_t vmid) "IOTLB invalidate vmid=%d" > > -smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64 > > +smmu_iotlb_inv_asid(int asid) "IOTLB invalidate asid=%d" > > +smmu_iotlb_inv_vmid(int vmid) "IOTLB invalidate vmid=%d" > > +smmu_iotlb_inv_iova(int asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64 > > smmu_inv_notifiers_mr(const char *name) "iommu mr=%s" > > -smmu_iotlb_lookup_hit(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" > > -smmu_iotlb_lookup_miss(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" > > -smmu_iotlb_insert(uint16_t asid, uint16_t vmid, uint64_t addr, uint8_t tg, uint8_t level) "IOTLB ++ asid=%d vmid=%d addr=0x%"PRIx64" tg=%d level=%d" > > +smmu_iotlb_lookup_hit(int asid, int vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" > > +smmu_iotlb_lookup_miss(int asid, int vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d" > > +smmu_iotlb_insert(int asid, int vmid, uint64_t addr, uint8_t tg, uint8_t level) "IOTLB ++ asid=%d vmid=%d addr=0x%"PRIx64" tg=%d level=%d" > > > > # smmuv3.c > > smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)" > > @@ -48,12 +48,12 @@ smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t p > > smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid=0x%x (hits=%d, misses=%d, hit rate=%d)" > > smmuv3_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d" > > smmuv3_cmdq_tlbi_nh(void) "" > > -smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d" > > -smmuv3_cmdq_tlbi_s12_vmid(uint16_t vmid) "vmid=%d" > > +smmuv3_cmdq_tlbi_nh_asid(int asid) "asid=%d" > > +smmuv3_cmdq_tlbi_s12_vmid(int vmid) "vmid=%d" > > smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x" > > smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s" > > smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s" > > -smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint16_t vmid, uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=%s asid=%d vmid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64 > > +smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=%s asid=%d vmid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64 > > > > # strongarm.c > > strongarm_uart_update_parameters(const char *label, int speed, char parity, int data_bits, int stop_bits) "%s speed=%d parity=%c data=%d stop=%d" > > diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h > > index 5944735632..96eb017e50 100644 > > --- a/include/hw/arm/smmu-common.h > > +++ b/include/hw/arm/smmu-common.h > > @@ -84,7 +84,7 @@ typedef struct SMMUS2Cfg { > > bool record_faults; /* Record fault events (S2R) */ > > uint8_t granule_sz; /* Granule page shift (based on S2TG) */ > > uint8_t eff_ps; /* Effective PA output range (based on S2PS) */ > > - uint16_t vmid; /* Virtual Machine ID (S2VMID) */ > > + int vmid; /* Virtual Machine ID (S2VMID) */ > > uint64_t vttb; /* Address of translation table base (S2TTB) */ > > } SMMUS2Cfg; > > > > @@ -108,7 +108,7 @@ typedef struct SMMUTransCfg { > > uint64_t ttb; /* TT base address */ > > uint8_t oas; /* output address width */ > > uint8_t tbi; /* Top Byte Ignore */ > > - uint16_t asid; > > + int asid; > > SMMUTransTableInfo tt[2]; > > /* Used by stage-2 only. */ > > struct SMMUS2Cfg s2cfg; > > @@ -132,8 +132,8 @@ typedef struct SMMUPciBus { > > > > typedef struct SMMUIOTLBKey { > > uint64_t iova; > > - uint16_t asid; > > - uint16_t vmid; > > + int asid; > > + int vmid; > > uint8_t tg; > > uint8_t level; > > } SMMUIOTLBKey; > > @@ -205,11 +205,11 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid); > > SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, > > SMMUTransTableInfo *tt, hwaddr iova); > > void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry); > > -SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iova, > > +SMMUIOTLBKey smmu_get_iotlb_key(int asid, int vmid, uint64_t iova, > > uint8_t tg, uint8_t level); > > void smmu_iotlb_inv_all(SMMUState *s); > > -void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); > > -void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid); > > +void smmu_iotlb_inv_asid(SMMUState *s, int asid); > > +void smmu_iotlb_inv_vmid(SMMUState *s, int vmid); > > void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova, > > uint8_t tg, uint64_t num_pages, uint8_t ttl); > > > Reviewed-by: Eric Auger > > Eric >