Re: [PATCH 0/4] Add support for Zhaoxin Yongfeng CPU model and other improvements

[Zhao Liu <zhao1.liu@intel.com>]

Hi EwanHai,

On Tue, Jun 25, 2024 at 05:19:01AM -0400, EwanHai wrote:
> Date: Tue, 25 Jun 2024 05:19:01 -0400
> From: EwanHai <ewanhai-oc@zhaoxin.com>
> Subject: [PATCH 0/4] Add support for Zhaoxin Yongfeng CPU model and other
>  improvements
> X-Mailer: git-send-email 2.34.1
> 
> This patch series introduces support for the Zhaoxin Yongfeng CPU model and includes
> some improvements and updates related to Zhaoxin and VIA CPUs. The changes ensure that
> QEMU can correctly identify and emulate Zhaoxin CPUs, providing accurate functionality
> and performance characteristics.
> 
>
> ### Summary of Changes
> 
> EwanHai (4):
>   target/i386: Add support for Zhaoxin/VIA CPU vendor identification
>   target/i386: Add CPUID leaf 0xC000_0001 EDX definitions
>   target/i386: Introduce Zhaoxin Yongfeng CPU model
>   target/i386: Update CMPLegacy handling for Zhaoxin and VIA CPUs
> 
>  target/i386/cpu.c | 130 ++++++++++++++++++++++++++++++++++++++++++++--
>  target/i386/cpu.h |  38 ++++++++++++++
>  2 files changed, 165 insertions(+), 3 deletions(-)
> 
> ### Known Bugs
> 
> 1. Issue with VMX Preemption Timer Rate on Yongfeng CPU:
>    - Description: On Yongfeng CPUs, the VMX preemption timer rate is 128, meaning that
>      bits 4:0 of MSR_IA32_VMX_MISC_CTLS should be set to 7. However, due to Intel's rate
>      being 5, the Linux kernel has hardcoded this value as 5:
>      `#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5`
>    - Impact: This discrepancy can cause incorrect behavior in the VMX preemption timer on
>      Yongfeng CPUs.
>    - Workaround: A patch to correct this issue in the Linux kernel is currently being
>      prepared and will be submitted soon.
>  

Thanks for your patch. Is there some spec/datasheet link that people can
refer to?

Regards,
Zhao