From: Nicolin Chen <nicolinc@nvidia.com>
To: Eric Auger <eric.auger@redhat.com>
Cc: <peter.maydell@linaro.org>, <shannon.zhaosl@gmail.com>,
<mst@redhat.com>, <imammedo@redhat.com>, <anisinha@redhat.com>,
<peterx@redhat.com>, <qemu-arm@nongnu.org>,
<qemu-devel@nongnu.org>, <jgg@nvidia.com>,
<shameerali.kolothum.thodi@huawei.com>, <jasowang@redhat.com>,
"Andrea Bolognani" <abologna@redhat.com>
Subject: Re: [PATCH RFCv1 05/10] hw/arm/virt: Add VIRT_NESTED_SMMU
Date: Tue, 9 Jul 2024 10:59:30 -0700 [thread overview]
Message-ID: <Zo16gnKKxXFg4LLE@Asurada-Nvidia> (raw)
In-Reply-To: <9c3e95c2-1035-4a55-89a3-97165ef32f18@redhat.com>
On Tue, Jul 09, 2024 at 03:26:58PM +0200, Eric Auger wrote:
> > @@ -1580,12 +1647,33 @@ static void create_pcie(VirtMachineState *vms)
> > qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
> > create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
> >
> > - if (vms->iommu) {
> > + /* Build PCI Expander Bridge + Root Port from the top of PCI_BUS_MAX */
> > + if (vms->num_nested_smmus) {
> > + /* VIRT_NESTED_SMMU must hold all vSMMUs */
> > + g_assert(vms->num_nested_smmus <=
> > + vms->memmap[VIRT_NESTED_SMMU].size / SMMU_IO_LEN);
> > +
> > + vms->nested_smmu_phandle = g_new0(uint32_t, vms->num_nested_smmus);
> > +
> > + for (i = 0; i < vms->num_nested_smmus; i++) {
> > + DeviceState *smmu_dev;
> > + PCIBus *pxb_bus;
> > +
> > + pxb_bus = create_pcie_expander_bridge(vms, i);
> > + g_assert(pxb_bus);
> > +
> > + vms->nested_smmu_phandle[i] = qemu_fdt_alloc_phandle(ms->fdt);
> > + smmu_dev = create_nested_smmu(vms, pxb_bus, i);
> > + g_assert(smmu_dev);
> > +
> > + qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map", 0x0,
> > + vms->nested_smmu_phandle[i], 0x0, 0x10000);
> I think libvirt is supposed to create the pcie bus topology instead and
> it shall not be created by qemu behind the scene.
> The pcie elements you create here are not visible to libvirt and I guess
> they may collide with elements explicitly created by libvirt at a given
> pci bdf.
Yea, the bdf conflict is a concern. So I allocated the bdf list
from the top of the bus number... one of the reasons of doing
this is to ease users so they don't need to deal with the over-
complicated topology. I will try libvirt and see how it goes.
> I think it would make more sense to be able to attach an smmu instance
> to a given pci root or pxb either by adding an iommu id to a given
> pxb-pcie option
>
> -device
> pxb-pcie,bus_nr=100,id=pci.12,numa_node=0,bus=pcie.0,addr=0x3,iommu=<id>
> or
> adding a list of pxb ids to the iommu option. It is unfortunate the
> iommu option is a machine option.
Yes. I had thought about that too, but the virt-machine code
creates all the instance at this moment...
> platform bus framework could be considered to dynamically allocate them
> using the -device option. This has been used along with dt generation
> but with ACPI this would need to be studied. However at the time the
> smmu was integrated the machine option was prefered.
>
> Maybe using the 1st option would allow to infer that if there are
> different iommu ids this implies that several IOMMU instances need to be
> created.
Yea, I like the idea of creating iommu instance with a "-device"
string.
One more question. Let's say we have 2 smmus/pxb-buses:
[ pxb0] <---> vSMMU0/pSMMU0 [ devA, devB, devC ]
[ pxb1] <---> vSMMU1/pSMMU1 [ devD, devE, devF ]
How would a user know that devA/devB should be attached to pxb0
without doing like devA->pxb0 and devB->pxb1? Should QEMU just
error out until the user associate them correctly? Or they may
rely on libvirt to figure that out, i.e. moving the iommu node
matching from QEMU to libvirt?
Thanks
Nicolin
next prev parent reply other threads:[~2024-07-09 18:00 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-26 0:28 [PATCH RFCv1 00/10] hw/arm/virt: Add multiple nested SMMUs Nicolin Chen
2024-06-26 0:28 ` [PATCH RFCv1 01/10] hw/arm/virt-acpi-build: Add IORT RMR regions to handle MSI nested binding Nicolin Chen via
2024-06-26 0:28 ` Nicolin Chen
2024-06-26 0:28 ` [PATCH RFCv1 02/10] hw/arm/virt: Add iommufd link to virt-machine Nicolin Chen via
2024-06-26 0:28 ` Nicolin Chen
2024-07-09 9:11 ` Eric Auger
2024-07-09 16:59 ` Nicolin Chen
2024-07-09 17:06 ` Eric Auger
2024-07-09 17:18 ` Nicolin Chen
2024-07-10 2:32 ` Duan, Zhenzhong
2024-06-26 0:28 ` [PATCH RFCv1 03/10] hw/arm/virt: Get the number of host-level SMMUv3 instances Nicolin Chen
2024-07-09 9:20 ` Eric Auger
2024-07-09 17:11 ` Nicolin Chen
2024-07-09 17:22 ` Eric Auger
2024-07-09 18:02 ` Nicolin Chen
2024-06-26 0:28 ` [PATCH RFCv1 04/10] hw/arm/virt: Add an SMMU_IO_LEN macro Nicolin Chen
2024-06-26 0:28 ` [PATCH RFCv1 05/10] hw/arm/virt: Add VIRT_NESTED_SMMU Nicolin Chen
2024-07-09 13:26 ` Eric Auger
2024-07-09 17:59 ` Nicolin Chen [this message]
2024-07-11 15:48 ` Andrea Bolognani
2024-07-11 17:57 ` Jason Gunthorpe
2024-06-26 0:28 ` [PATCH RFCv1 06/10] hw/arm/virt: Assign vfio-pci devices to nested SMMUs Nicolin Chen
2024-07-09 13:32 ` Eric Auger
2024-06-26 0:28 ` [PATCH RFCv1 07/10] hw/arm/virt: Bypass iommu for default PCI bus Nicolin Chen
2024-06-26 0:28 ` [PATCH RFCv1 08/10] hw/arm/virt-acpi-build: Handle reserved bus number of pxb buses Nicolin Chen
2024-06-26 0:28 ` [PATCH RFCv1 09/10] hw/arm/virt-acpi-build: Build IORT with multiple SMMU nodes Nicolin Chen
2024-06-26 0:28 ` [PATCH RFCv1 10/10] hw/arm/virt-acpi-build: Enable ATS for nested SMMUv3 Nicolin Chen
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