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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(7416014)(82310400026)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2024 17:19:27.1940 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7bfcd287-79f0-47c6-ea0b-08dca03b494e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D4.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6738 Received-SPF: softfail client-ip=2a01:111:f400:7ea9::61c; envelope-from=nicolinc@nvidia.com; helo=NAM02-SN1-obe.outbound.protection.outlook.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.144, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: lFu28L9dV45W On Tue, Jul 09, 2024 at 07:06:50PM +0200, Eric Auger wrote: > On 7/9/24 18:59, Nicolin Chen wrote: > > Hi Eric, > > > > Thanks for the comments! > > > > On Tue, Jul 09, 2024 at 11:11:56AM +0200, Eric Auger wrote: > >> On 6/26/24 02:28, Nicolin Chen wrote: > >>> A nested SMMU must use iommufd ioctls to communicate with the host-level > >>> SMMU instance for 2-stage translation support. Add an iommufd link to the > >>> ARM virt-machine, allowing QEMU command to pass in an iommufd object. > >> If I am not wrong vfio devices are allowed to use different iommufd's > >> (although there is no real benefice). So this command line wouldn't > >> match with that option. > > I think Jason's remarks highlighted that FD should be one per VM: > > https://lore.kernel.org/qemu-devel/20240503141024.GE3341011@nvidia.com/ > OK I thought this was still envisionned althought not really meaningful. > By the way, please add Yi and Zhenzhong in cc since thre problematics > are connected I think. Yea. Yi/Zhenzhong, would you please shed some light on forwarding an iommufd handler to the intel_iommu code? IIRC, we did that at the beginning but removed it later? > >> Also while reading the commit msg it is not clear with the iommufd is > >> needed in the machine whereas the vfio iommufd BE generally calls those > >> ioctls. > > I think I forgot to revisit it. Both intel_iommu and smmu-common > > used to call iommufd_backend_connect() for counting, so there was > > a need to pass in the same iommufd handler to the viommu driver. > > For SMMU, since it is created in the virt code, we had to pass in > > with this patch. > > > > That being said, it looks like intel_iommu had removed that. So, > > likely we don't need an extra user counting for SMMU too. > OK at least it deserves some explanation about the "why" Yes, I agree that the commit message isn't good enough. Thanks Nicolin