From: Nicolin Chen <nicolinc@nvidia.com>
To: Will Deacon <will@kernel.org>
Cc: <robin.murphy@arm.com>, <joro@8bytes.org>, <jgg@nvidia.com>,
<thierry.reding@gmail.com>, <vdumpa@nvidia.com>,
<jonathanh@nvidia.com>, <linux-kernel@vger.kernel.org>,
<iommu@lists.linux.dev>, <linux-arm-kernel@lists.infradead.org>,
<linux-tegra@vger.kernel.org>
Subject: Re: [PATCH v9 4/6] iommu/arm-smmu-v3: Add CS_NONE quirk for CONFIG_TEGRA241_CMDQV
Date: Tue, 9 Jul 2024 11:29:46 -0700 [thread overview]
Message-ID: <Zo2Bmm0KfEBn2jMb@Asurada-Nvidia> (raw)
In-Reply-To: <ZowpGi/q7MeS5iYO@Asurada-Nvidia>
Hi Will,
On Mon, Jul 08, 2024 at 11:00:00AM -0700, Nicolin Chen wrote:
> On Mon, Jul 08, 2024 at 12:29:28PM +0100, Will Deacon wrote:
> > > With that, we cannot avoid an unconditional hard-coding tegra
> > > function call even if we switch to an impl design:
> > >
> > > +static int acpi_smmu_impl_init(u32 model, struct arm_smmu_device *smmu)
> > > +{
> > > + /*
> > > + * unconditional go through ACPI table to detect if there is a tegra241
> > > + * implementation that extends SMMU with a CMDQV. The probe() will fill
> > > + * the smmu->impl pointer upon success. Otherwise, fall back to regular
> > > + * SMMU CMDQ.
> > > + */
> > > + tegra241_impl_acpi_probe(smmu);
> >
> > In-line the minimal DSDT parsing to figure out if we're on a Tegra part.
> > If it's that bad, put it in a static inline in arm-smmu-v3.h.
>
> OK. How about the following?
>
> /* arm-smmu-v3.h */
> static inline void arm_smmu_impl_acpi_dsdt_probe(struct arm_smmu_device *smmu,
> struct acpi_iort_node *node)
> {
> tegra241_cmdqv_acpi_dsdt_probe(smmu, node);
> }
>
> /* arm-smmu-v3.c */
> static int arm_smmu_impl_acpi_probe(struct arm_smmu_device *smmu,
> struct acpi_iort_node *node)
> {
> /*
> * DSDT might holds some SMMU extension, so we have no option but to go
> * through ACPI tables unconditionally. This probe function should fill
> * the smmu->impl pointer upon success. Otherwise, just carry on with a
> * standard SMMU.
> */
> arm_smmu_impl_acpi_dsdt_probe(smmu, node);
>
> return 0;
> }
I have reworked my series and it looks like:
-------------------------------------------------------------
@ -627,9 +630,35 @@ struct arm_smmu_strtab_cfg {
u32 strtab_base_cfg;
};
+struct arm_smmu_impl {
+ int (*device_reset)(struct arm_smmu_device *smmu);
+ void (*device_remove)(struct arm_smmu_device *smmu);
+ struct arm_smmu_cmdq *(*get_secondary_cmdq)(struct arm_smmu_device *smmu,
+ u8 opcode);
+};
+
+#ifdef CONFIG_TEGRA241_CMDQV
+struct arm_smmu_device *
+tegra241_cmdqv_acpi_dsdt_probe(struct arm_smmu_device *smmu,
+ struct acpi_iort_node *node);
+#endif
+
+static inline struct arm_smmu_device *
+arm_smmu_impl_acpi_dsdt_probe(struct arm_smmu_device *smmu,
+ struct acpi_iort_node *node)
+{
+#ifdef CONFIG_TEGRA241_CMDQV
+ smmu = tegra241_cmdqv_acpi_dsdt_probe(smmu, node);
+#endif
+ return smmu;
+}
+
/* An SMMUv3 instance */
struct arm_smmu_device {
struct device *dev;
+ /* An SMMUv3 implementation */
+ const struct arm_smmu_impl *impl;
+
void __iomem *base;
void __iomem *page1;
-------------------------------------------------------------
One thing that I want to confirm is about the smmu pointer.
I implemented in the way that SMMUv2 driver does, i.e. the
passed-in SMMU pointer gets devm_realloc() to &cmdev->smmu.
Is it something you would prefer?
Thanks
Nicolin
next prev parent reply other threads:[~2024-07-09 18:30 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-12 21:45 [PATCH v9 0/6] Add Tegra241 (Grace) CMDQV Support (part 1/2) Nicolin Chen
2024-06-12 21:45 ` [PATCH v9 1/6] iommu/arm-smmu-v3: Make symbols public for CONFIG_TEGRA241_CMDQV Nicolin Chen
2024-06-12 21:45 ` [PATCH v9 2/6] iommu/arm-smmu-v3: Issue a batch of commands to the same cmdq Nicolin Chen
2024-06-12 21:45 ` [PATCH v9 3/6] iommu/arm-smmu-v3: Enforce arm_smmu_cmdq_build_sync_cmd Nicolin Chen
2024-06-12 21:45 ` [PATCH v9 4/6] iommu/arm-smmu-v3: Add CS_NONE quirk for CONFIG_TEGRA241_CMDQV Nicolin Chen
2024-07-02 17:43 ` Will Deacon
2024-07-02 18:19 ` Nicolin Chen
2024-07-02 18:49 ` Will Deacon
2024-07-02 19:47 ` Nicolin Chen
2024-07-02 20:10 ` Nicolin Chen
2024-07-05 15:27 ` Will Deacon
2024-07-05 18:10 ` Nicolin Chen
2024-07-06 0:32 ` Nicolin Chen
2024-07-08 11:31 ` Will Deacon
2024-07-08 18:02 ` Nicolin Chen
2024-07-08 11:29 ` Will Deacon
2024-07-08 11:43 ` Will Deacon
2024-07-08 18:05 ` Nicolin Chen
2024-07-08 17:59 ` Nicolin Chen
2024-07-09 18:29 ` Nicolin Chen [this message]
2024-06-12 21:45 ` [PATCH v9 5/6] iommu/arm-smmu-v3: Add in-kernel support for NVIDIA Tegra241 (Grace) CMDQV Nicolin Chen
2024-07-02 17:41 ` Will Deacon
2024-07-02 19:23 ` Nicolin Chen
2024-06-12 21:45 ` [PATCH v9 6/6] iommu/tegra241-cmdqv: Limit CMDs for guest owned VINTF Nicolin Chen
2024-06-28 19:26 ` [PATCH v9 0/6] Add Tegra241 (Grace) CMDQV Support (part 1/2) Pavel Machek
2024-06-28 21:29 ` Nicolin Chen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Zo2Bmm0KfEBn2jMb@Asurada-Nvidia \
--to=nicolinc@nvidia.com \
--cc=iommu@lists.linux.dev \
--cc=jgg@nvidia.com \
--cc=jonathanh@nvidia.com \
--cc=joro@8bytes.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=robin.murphy@arm.com \
--cc=thierry.reding@gmail.com \
--cc=vdumpa@nvidia.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.